CDP1871 데이터 시트보기 (PDF) - Intersil

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CDP1871

CMOS Keyboard Encoder

Intersil 

CDP1871A, CDP1871AC

VDD

100K

0.1µF

N0-N2

MRD

TPB

21

CONTROL

23

24

34

40

36

DEBOUNCE

CS1,

CS2,

CS3

11

D11

CS4

TPB

CDP1800-SERIES

CPU

CDP1871A

VDD SHIFT

39

SHIFT

1

D1

UP TO 11 SETS

OF 8 SWITCHES EACH

BUS0-BUS7

CONTROL

38

CONTROL

ALPHA LOCK

37

ALPHA

NORMAL

8 BIT DATA BUS

BUS0-BUS7

25 32

S1 12

S2 13

S3 14

S4 15

S5 16

S6 17

S7 18

S8 19

FIGURE 1. TYPICAL CDP1800 SERIES MICROPROCESSOR SYSTEM USING THE CDP1871A

CS1 21

CS2 22

CS3 23

CS4 24

TPB 34

CS

SCAN CLOCK THREE-STAGE

SCAN COUNTER

CONTROL

LOGIC

KEY

VDD

DETECT

F/F

RX DEBOUNCE

36

CX

RN

FIVE-STAGE

SCAN COUNTER

BUS ENABLE

C1-C3

C4-C8

THREE-STATE

OUTPUT

BUFFERS

25 BUS 0

32 BUS 7

VDD 40

VSS 20

DA 33

RPT 35

STATUS

LATCHES

KEY DOWN

DETECT

LATCH

1 OF 8

RPD MUX

RPD

FROM

KEY BOARD

12

19

SENSE

LINES

II

DECODER/

DRIVERS

TO

KEY BOARD

1

11

DRIVE

DI LINES DII

FIGURE 2. CDP1871A BLOCK DIAGRAM

RPD

RPD

37

39

38

ALPHA SHIFT CONTROL

4-67

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