CS43L42
LRCK
SCLK
SDATA
t slrd
t sdlrs
t slrs
t sclkh
t sclkl
t sdh
LRCK
SDATA
*IN TE R N A L
SCLK
t sclkr
t s d lrs t sd h
t sc lkw
Figure 1. External Serial Mode Input Timing
Figure 2. Internal Serial Mode Input Timing
*The SCLK pulses shown are internal to the CS43L42.
LRCK
MCLK
1
N
N
2
*INTERNAL SCLK
SDATA
Figure 3. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS43L42.
N equals MCLK divided by SCLK
DS481PP2
11