CXA3067M 데이터 시트보기 (PDF) - Sony Semiconductor
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CXA3067M Datasheet PDF : 24 Pages
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CXA3067M
Description of PLL Block
1. The followings “channel No.” can be selected through the combination of the conditions of pins 1, 29 and 30
(FSET 1; 2; 3).
FSET conditions have 3 states (OPEN, Hi, Low).
Channel Selection
Channel No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Local
OSC frequency
[MHz]
42.65
83.70
98.20
100.00
108.20
117.20
117.80
119.20
133.40
139.20
168.70
180.20
211.25
219.10
312.70
Note) OPEN : No connect
L : Connect to GND
H : Connect to VCC
Receiving
frequency
[MHz]
53.55
73.00
87.50
89.30
97.50
106.50
128.50
108.50
122.70
128.50
158.00
169.50
221.95
229.80
302.00
FSET 1
OPEN
L
H
OPEN
L
H
OPEN
L
H
OPEN
L
H
OPEN
L
H
FSET 2
OPEN
OPEN
OPEN
L
L
L
H
H
H
OPEN
OPEN
OPEN
L
L
L
FSET 3
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
L
L
L
L
L
L
—14—
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