CY7C1061AV33-12ZXC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1061AV33-12ZXC Datasheet PDF : 10 Pages
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CY7C1061AV33
AC Switching Characteristics (Over the Operating Range) [6]
Parameter
Description
Read Cycle
tpower
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Write Cycle [10, 11]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
VCC(typical) to the first access [7]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE1 LOW/CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z [8]
CE1 LOW/CE2 HIGH to Low-Z [8]
CE1 HIGH/CE2 LOW to High-Z [8]
CE1 LOW/CE2 HIGH to Power Up [9]
CE1 HIGH/CE2 LOW to Power Down [9]
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
Write Cycle Time
CE1 LOW/CE2 HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low-Z [8]
WE LOW to High-Z [8]
Byte Enable to End of Write
–10
Min
Max
1
10
10
3
10
5
1
5
3
5
0
10
5
1
5
10
7
7
0
0
7
5.5
0
3
5
7
–12
Unit
Min
Max
1
ms
12
ns
12
ns
3
ns
12
ns
6
ns
1
ns
6
ns
3
ns
6
ns
0
ns
12
ns
6
ns
1
ns
6
ns
12
ns
8
ns
8
ns
0
ns
0
ns
8
ns
6
ns
0
ns
3
ns
6
ns
8
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in (a) of the “AC Test Loads and Waveforms [5]” on
page 3, unless specified otherwise.
7.
8.
This part has
tHZOE, tHZCE,
a voltage regulator that steps down the voltage from 3V to
tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified
2V internally. tpower time
with a load capacitance
must be provided initially before a Read/Write operation is started.
of 5 pF as in (b) of “AC Test Loads and Waveforms [5]” on page 3.
Transition is measured ±200 mV from steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal Write time of the memory is defined by the overlap of CE1 LOW (CE2 HIGH) and WE LOW. Chip enables must be active and WE and byte enables
must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to
the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05256 Rev. *G
Page 4 of 10
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