CY7C1324H-133AXI 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1324H-133AXI

2-Mbit (128K x 18) Flow-Through Sync SRAM

Cypress Semiconductor 

CY7C1324H

Timing Diagrams

Read Cycle Timing[15]

tCYC

CLK

ADSP

ADSC

t CH t CL

tADS tADH

tADS tADH

tAS tAH

ADDRESS

GW, BWE,BW

[A:B]

CE

A1

A2

t WES tWEH

tCES tCEH

t

ADVS

t ADVH

Deselect Cycle

ADV

ADV suspends burst.

OE

Data Out (Q)

High-Z

tOEV

tCLZ

tCDV

tOEHZ

Q(A1)

Single READ

tOELZ

tCDV

tDOH

Q(A2) Q(A2 + 1)

Q(A2 + 2)

DON’T CARE

BURST

READ

UNDEFINED

Q(A2 + 3)

tCHZ

Q(A2) Q(A2 + 1) Q(A2 + 2)

Burst wraps around

to its initial state

Note:

15. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 001-00208 Rev. *B

Page 10 of 15

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