CY7C1324H-133AXI 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1324H-133AXI

2-Mbit (128K x 18) Flow-Through Sync SRAM

Cypress Semiconductor 

Timing Diagrams (continued)

Write Cycle Timing[15, 16]

tCYC

CY7C1324H

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A:B]

GW

CE

ADV

t

CH

t CL

tADS tADH

tADS tADH

tAS tAH

A1

A2

Byte write signals are ignored for first cycle when

ADSP initiates burst.

tCES tCEH

t

WES

t

WEH

ADSC extends burst.

tADS tADH

A3

tWES tWEH

tADVS tADVH

ADV suspends burst.

OE

tDS t DH

Data in (D)

Data Out (Q)

High-Z

D(A1)

tOEHZ

D(A2)

D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3)

BURST READ

Single WRITE

BURST WRITE

DON’T CARE UNDEFINED

Note:

16. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.

D(A3)

D(A3 + 1) D(A3 + 2)

Extended BURST WRITE

Document #: 001-00208 Rev. *B

Page 11 of 15

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