CY7C63000 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C63000

Universal Serial Bus Microcontroller

Cypress Semiconductor 

PRELIMINARY

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

Table 5-3. Interrupt Vector Assignments

Interrupt Vector Number

0

1

2

3

4

5

6

7

ROM Address

0x00

0x02

0x04

0x06

0x08

0x0A

0x0C

0x0E

Function

Reset

128 µs timer interrupt

1.024 ms timer interrupt

USB end point 0 interrupt

USB end point 1 interrupt

Reserved

GPIO interrupt

Wake-up interrupt

5.8.1 Interrupt Latency

Interrupt latency can be calculated from the following equation:

Interrupt Latency = (Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) +

(5 clock cycles for the JMP instruction)

For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the

Interrupt Service Routine will execute a min. of 16 clocks (1+10+5) or a max. of 20 clocks (5+10+5) after the interrupt is issued.

The interrupt latches are sampled at the rising edge of the last clock cycle in the current instruction.

5.8.2 GPIO Interrupt

The General Purpose I/O interrupts are generated by signal transitions at the Port 0 and Port 1 I/O pins. GPIO interrupts are edge

sensitive with programmable interrupt polarities. Setting a bit HIGH in the Port Pull-up Register (see Figure 5-10 and 5-11) selects

a LOW to HIGH interrupt trigger for the corresponding port pin. Setting a bit LOW activates a HIGH to LOW interrupt trigger. Each

GPIO interrupt is maskable on a per-pin basis by a dedicated bit in the Port Interrupt Enable Register. Writing a “1” enables the

interrupt. Figure 5-17 and Figure 5-18 illustrate the format of the Port Interrupt Enable Registers for Port 0 and Port 1 located at

I/O address 0x04 and 0x05 respectively. These write only registers are cleared during reset, thus disabling all GPIO interrupts.

7

W

P0.7 Int En

6

5

4

3

2

1

W

W

W

W

W

W

P0.6 Int En P0.5 Int En P0.4 Int En P0.3 Int En P0.2 Int En P0.1 Int En

Figure 5-17. Port 0 Interrupt Enable Register (Address 0x04)

0

W

P0.0 Int En

7

W

P1.7 Int En

6

W

P1.6 Int En

5

W

P1.5 Int En

4

W

P1.4 Int En

3

W

P1.3 Int En

2

W

P1.2 Int En

1

W

P1.1 Int En

0

W

P1.0 Int En

Figure 5-18. Port 1 Interrupt Enable Register (Address 0x05)

A block diagram of the GPIO interrupt logic is shown in Figure 5-19. The bit setting in the Port Pull-up Register selects the interrupt

polarity. If the selected signal polarity is detected on the I/O pin a HIGH signal is generated. If the Port Interrupt Enable bit for this

pin is HIGH and no other port pins are requesting interrupts, then the 12-input OR gate will issue a LOW to HIGH signal to clock

the GPIO interrupt flip flop. The output of the flip flop is further qualified by the Global GPIO Interrupt Enable bit before it is

processed by the Interrupt Priority Encoder. Both the GPIO interrupt flip flop and the Global GPIO Enable bit are cleared during

GPIO interrupt acknowledge by on-chip hardware.

16

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