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CY7C63001A-SC

Universal Serial Bus Microcontroller

Cypress Semiconductor 

FOR

FOR

CY7C63000A/CY7C63001A

CY7C63100A/CY7C63101A

the Interrupt Priority Encoder. Both the GPIO interrupt flip-flop and the Global GPIO Enable bit are cleared by on-chip hardware

during GPIO interrupt acknowledge.

GPIO

Pin

Port

Pull-Up

Register

1=L→H

0=HÆL

M

U

X

OR Gate

(1 input per

GPIO pin)

GPIO Interrupt

Flip-Flop

ID Q

CLR

1 = Enable

0 = Disable

Port Interrupt

Enable Register

Interrupt

Acknowledge

CLR

1 = Enable

0 = Disable

Global

GPIO Interrupt

Enable

(Bit 6, Register 0x20)

Interrupt

Priority

Encoder

IRQ

Interrupt

Vector

Figure 5-19. GPIO Interrupt Logic Block Diagram

Note: If one port pin triggers an interrupt, no other port pin can cause a GPIO interrupt until the port pin that triggered the interrupt

has returned to its inactive (non-trigger) state or until its corresponding port interrupt enable bit is cleared (these events ‘reset’

the clock of the GPIO Interrupt flip-flop, which must be ‘reset’ to ‘0’ before another GPIO interrupt event can ‘clock’ the GPIO

Interrupt flip-flop and produce an IRQ).

Note: If the port pin that triggered an interrupt is held in its active (trigger) state while its corresponding port interrupt enable bit

is cleared and then set, a GPIO interrupt event occurs as the GPIO Interrupt flip-flop clock transitions from ‘1’ to ‘0’ and then back

to ‘1’ (please refer to Figure 5-19). The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt

Enable Registers are not cleared during the interrupt acknowledge process. When a GPIO interrupt is serviced, the ISR must

poll the ports to determine which pin caused the interrupt.

5.8.3 USB Interrupt

A USB Endpoint 0 interrupt is generated after the host has written data to Endpoint 0 or after the USB Controller has transmitted

a packet from Endpoint 0 and receives an ACK from the host. An OUT packet from the host which is NAKed by the USB Controller

does not generate an interrupt. This interrupt is masked by the USB EP0 Interrupt Enable bit (bit 3) of the Global Interrupt Enable

Register.

A USB Endpoint 1 interrupt is generated after the USB Controller has transmitted a packet from Endpoint 1 and has received an

ACK from the host. This interrupt is masked by the USB EP1 Interrupt Enable bit (bit 4) of the Global Interrupt Enable Register.

5.8.4 Timer Interrupt

There are two timer interrupts: the 128-µs interrupt and the 1.024-ms interrupt. They are masked by bits 1 and 2 of the Global

Interrupt Enable Register respectively. The user should disable both timer interrupts before going into the suspend mode to avoid

possible conflicts from timer interrupts occurring just as suspend mode is entered.

5.8.5 Wake-Up Interrupt

A wake-up interrupt is generated when the Cext pin goes HIGH. This interrupt is latched in the interrupt controller. It can be

masked by the Wake-up Interrupt Enable bit (bit 7) of the Global Interrupt Enable Register. This interrupt can be used to perform

periodic checks on attached peripherals when the USB Controller is placed in the low-power suspend mode. See the Instant-On

Feature section for more details.

5.9 USB Engine

The USB engine includes the Serial Interface Engine (SIE) and the low-speed USB I/O transceivers. The SIE block performs

most of the USB interface functions with only minimal support from the microcontroller core. Two endpoints are supported.

Endpoint 0 is used to receive and transmit control (including setup) packets while Endpoint 1 is only used to transmit data packets.

Document #: 38-08026 Rev. **

Page 16 of 31

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