CY7C63001A-SC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C63001A-SC Datasheet PDF : 31 Pages
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FOR
FOR
CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A
0
0
0
0
0
0
0
0
Figure 5-21. USB Endpoint 0 RX Register (Address 0x14)
This is a read/write register located at I/O address 0x14. Any write to this register clears all bits except bit 3 which remains
unchanged. All bits are cleared during reset.
Bit 0 is set to 1 when a SETUP token for Endpoint 0 is received. Once set to a 1, this bit remains HIGH until it is cleared by an
I/O write or a reset. While the data following a SETUP is being received by the USB engine, this bit is not cleared by an I/O write.
User firmware writes to the USB FIFOs are disabled when bit 0 is set. This prevents SETUP data from being overwritten.
Bits 1 and 2 are updated whenever a valid token is received on Endpoint 0. Bit 1 is set to 1 if an OUT token is received and
cleared to 0 if any other token is received. Bit 2 is set to 1 if an IN token is received and cleared to 0 if any other token is received.
Bit 3 shows the Data Toggle status of DATA packets received on Endpoint 0. This bit is updated for DATA following SETUP tokens
and for DATA following OUT tokens if Stall (bit 5 of 0x10) is not set and either EnableOuts or StatusOuts (bits 3 and 4 of 0x13)
are set.
Bits 4 to 7 are the count of the number of bytes received in a DATA packet. The two CRC bytes are included in the count, so the
count value is two greater than the number of data bytes received. The count is always updated and the data is always stored in
the FIFO for DATA packets following a SETUP token. The count for DATA following an OUT token is updated if Stall (bit 5 of 0x10)
is 0 and either EnableOuts or StatusOuts (bits 3 and 4 of 0x13) are 1. The DATA following an OUT is written into the FIFO if
EnableOuts is set to 1 and Stall and StatusOuts are 0.
A maximum of 8 bytes are written into the Endpoint 0 FIFO. If there are less than 8 bytes of data the CRC is written into the FIFO.
Due to register space limitations, the Receive Data Invalid bit is located in the USB Endpoint 0 TX Configuration Register. Refer
to the Endpoint 0 Transmit section for details. This bit is set by the SIE if an error is detected in a received DATA packet.
Table 5-4 summarizes the USB Engine response to SETUP and OUT transactions on Endpoint 0. In the Data Packet column
‘Error’ represents a packet with a CRC, PID or bit-stuffing error, or a packet with more than 8 bytes of data. ‘Valid’ is a packet
without an Error. ‘Status’ is a packet that is a valid control read Status stage, while ‘N/Status’ is not a correct Status stage (see
section 5.9.4). The ‘Stall’ bit is described in Section 5.9.2.2. The ‘StatusOuts’ and ‘EnableOuts’ bits are described in section 5.9.4.
Table 5-4. USB Engine Response to SETUP and OUT Transactions on Endpoint 0
Control Bit Settings
Stall Status Out Enable Out
-
-
-
-
-
-
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
1
0
Received Packets
Token
Type
Data
Packet
SETUP
Valid
SETUP
Error
OUT
Valid
OUT
Error
OUT
Valid
OUT
Error
OUT
Valid
OUT
Error
OUT
Status
OUT
N/Status
OUT
Error
FIFO Write
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
USB Engine Response
Toggle
Update
Count
Update
Interrupt
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Reply
ACK
None
ACK
None
NAK
None
STALL
None
ACK
STALL
None
5.9.2.2 Endpoint 0 Transmit
The USB Endpoint 0 TX Register located at I/O address 0x10 controls data transmission from Endpoint 0 (see Figure 5-22). This
is a read/write register. All bits are cleared during reset.
b7
INEN
R/W
b6
b5
b4
b3
b2
b1
DATA1/0
STALL
ERR
COUNT3
COUNT2
COUNT1
R/W
R/W
R/W
R/W
R/W
R/W
Figure 5-22. USB Endpoint 0 TX Configuration Register (Address 0x10)
b0
COUNT0
R/W
Document #: 38-08026 Rev. **
Page 18 of 31
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