CY7C63001A-SC 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C63001A-SC

Universal Serial Bus Microcontroller

Cypress Semiconductor 

FOR

FOR

CY7C63000A/CY7C63001A

CY7C63100A/CY7C63101A

Bit 4 is used to enable the receiving of Endpoint 0 OUT packets. When this bit is set to 1, the data from an OUT transaction is

written into the Endpoint 0 FIFO. If this bit is 0, data is not written to the FIFO and the SIE responds with a NAK. This bit is cleared

following a SETUP or ACKed OUT transaction. Note: After firmware decodes a SETUP packet and prepares for a subsequent

OUT transaction by setting bit 4, bit 4 is not cleared until the hand-shake phase of an ACKed OUT transaction (a NAKed OUT

transaction does not clear this bit).

5.10 USB Physical Layer Characteristics

The following section describes the CY7C630/1XXA compliance to the Chapter 7 Electrical section of the USB Specification,

Revision 1.1. The section contains all signaling, power distribution, and physical layer specifications necessary to describe a low-

speed USB function.

5.10.1 Low-Speed Driver Characteristics

The CY7C630/1XXA devices use a differential output driver to drive the Low-speed USB data signal onto the USB cable, as

shown in Figure 5-25. The output swings between the differential HIGH and LOW state are well balanced to minimize signal skew.

Slew rate control on the driver minimizes the radiated noise and cross talk on the USB cable. The driver’s outputs support

three-state operation to achieve bidirectional half duplex operation. The CY7C630/1XXA driver tolerates a voltage on the signal

pins of –0.5V to 3.8V with respect to local ground reference without damage. The driver tolerates this voltage for 10.0 µs while

the driver is active and driving, and tolerates this condition indefinitely when the driver is in its high-impedance state.

A low-speed USB connection is made through an unshielded, untwisted wire cable a maximum of 3 meters in length. The rise

and fall time of the signals on this cable are well controlled to reduce RFI emissions while limiting delays, signaling skews and

distortions. The CY7C630/1XXA driver reaches the specified static signal levels with smooth rise and fall times, resulting in

minimal reflections and ringing when driving the USB cable. This cable and driver are intended to be used only on network

segments between low-speed devices and the ports to which they are connected.

One Bit

Time

(1.5Mb/s)

VSE (max)

Driver

Signal Pins

VSE (min)

VSS

Signal pins

pass output

spec levels

with minimal

reflections and

ringing

Figure 5-25. Low-speed Driver Signal Waveforms

5.10.2 Receiver Characteristics

The CY7C630/1XXA has a differential input receiver which is able to accept the USB data signal. The receiver features an input

sensitivity of at least 200 mV when both differential data inputs are in the range of at least 0.8V to 2.5V with respect to its local

ground reference. This is the common mode input voltage range. Proper data reception is also guaranteed when the differential

data lines are outside the common mode range, as shown in Figure 5-26. The receiver tolerates static input voltages between

–0.5V and 3.8V with respect to its local ground reference without damage. In addition to the differential receiver, there is a

Document #: 38-08026 Rev. **

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