CY7C63001A-SC 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C63001A-SC Datasheet PDF : 31 Pages
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FOR
FOR
CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A
single-ended receiver for each of the two data lines. The single-ended receivers have a switching threshold between 0.8V and
2.0V (TTL inputs).
1.0
0.8
0.6
0.4
0.2
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
Common Mode Input Voltage (volts)
Figure 5-26. Differential Input Sensitivity Over Entire Common Mode Range
5.11 External USB Pull-Up Resistor
The USB system specifies that a pull-up resistor be connected on the D– pin of low-speed peripherals as shown in Figure 5-27.
To meet the USB 1.1 spec (section 7.1.6), which states that the termination must charge the D– line from 0 to 2.0 V in 2.5 µs, the
total load capacitance on the D+/D– lines of the low-speed USB device (Cypress device capacitance + PCB trace capacitance
+ integrated cable capacitance) must be less than 250 pF. As Cypress D+/D– transceiver input capacitance is 20pF max, up to
230 pF of capacitance is allowed for in the low speed device’s integrated cable and PCB. If the cable + PCB capacitance on the
D+/D– lines will be greater than approximately 230 pF, an external 3.3V regulator must be used as shown in Figure 5-28.
Switches,
Devices, Etc.
For Cext
Wake-up Mode
Port0
Port0
Switches,
Devices, Etc.
Port1
VSS
VPP
CEXT
XTALIN
Port1
D+
D–
VCC
XTALOUT
6-MHz 0.1µF
Resonator
7.5kW±1%
+4.35V (min)
4.7 µF
Figure 5-27. Application Showing 7.5kΩ±1% Pull-Up Resistor
Switches,
Devices, Etc.
For Cext
Wake-up Mode
Port0
Port0
Port1
VSS
VPP
CEXT
XTALIN
Port1
D+
D–
VCC
XTALOUT
Switches,
Devices, Etc.
6-MHz 0.1µF
Resonator
+3.3V 3.3V
Reg
0.1 µF
1.5±kW
+4.35V (min.)
4.7 µF
Document #: 38-08026 Rev. **
Page 21 of 31
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