CY8C3665PVI-008(2010) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY8C3665PVI-008
(Rev.:2010)

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PRELIMINARY

PSoC® 3: CY8C36 Family Datasheet

Table 4-2. Logical Instructions (continued)

ORL

ORL

Mnemonic

A,#data

Direct, A

Description

OR immediate data to accumulator

OR accumulator to direct byte

ORL Direct, #data

XRL A,Rn

XRL A,Direct

OR immediate data to direct byte

XOR register to accumulator

XOR direct byte to accumulator

XRL A,@Ri

XRL A,#data

XRL Direct, A

XOR indirect RAM to accumulator

XOR immediate data to accumulator

XOR accumulator to direct byte

XRL Direct, #data

CLR A

CPL A

XOR immediate data to direct byte

Clear accumulator

Complement accumulator

RL A

RLC A

RR A

Rotate accumulator left

Rotate accumulator left through carry

Rotate accumulator right

RRC A

SWAP A

Rotate accumulator right though carry

Swap nibbles within accumulator

Bytes

2

2

3

1

2

1

2

2

3

1

1

1

1

1

1

1

Cycles

2

3

3

1

2

2

2

3

3

1

1

1

1

1

1

1

4.3.1.3 Data Transfer Instructions

The data transfer instructions are of three types: the core RAM,

xdata RAM, and the lookup tables. The core RAM transfer

includes transfer between any two core RAM locations or SFRs.

These instructions can use direct, indirect, register, and

immediate addressing. The xdata RAM transfer includes only the

transfer between the accumulator and the xdata RAM location.

It can use only indirect addressing. The lookup tables involve

nothing but the read of program memory using the Indexed

addressing mode. Table 4-3 lists the various data transfer

instructions available.

4.3.1.4 Boolean Instructions

The 8051 core has a separate bit-addressable memory location.

It has 128 bits of bit addressable RAM and a set of SFRs that are

bit addressable. The instruction set includes the whole menu of

bit operations such as move, set, clear, toggle, OR, and AND

instructions and the conditional jump instructions. Table 4-4 on

page 14 lists the available Boolean instructions.

Table 4-3. Data Transfer Instructions

Mnemonic

MOV A,Rn

Description

Move register to accumulator

Bytes

1

Cycles

1

MOV A,Direct

MOV A,@Ri

MOV A,#data

Move direct byte to accumulator

Move indirect RAM to accumulator

Move immediate data to accumulator

2

2

1

2

2

2

MOV

MOV

MOV

Rn,A

Rn,Direct

Rn, #data

Move accumulator to register

Move direct byte to register

Move immediate data to register

1

1

2

3

2

2

MOV

MOV

MOV

Direct, A

Direct, Rn

Direct, Direct

Move accumulator to direct byte

Move register to direct byte

Move direct byte to direct byte

2

2

2

2

3

3

MOV

MOV

MOV

Direct, @Ri

Direct, #data

@Ri, A

Move indirect RAM to direct byte

Move immediate data to direct byte

Move accumulator to indirect RAM

2

3

3

3

1

2

Document Number: 001-53413 Rev. *I

Page 13 of 112

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