CY8C5488PVI-077 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY8C5488PVI-077 Datasheet PDF : 93 Pages
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PRELIMINARY
PSoC®5: CY8C54 Family Data Sheet
Figure 2-1. 48-Pin SSOP Part Pinout [2]
(SIO) P12[2] 1
(SIO) P12[3] 2
(OpAmp2out, GPIO) P0[0] 3
(OpAmp0out, GPIO) P0[1] 4
(OpAmp0+, GPIO) P0[2] 5
(OpAmp0-/Extref0, GPIO) P0[3] 6
Vddio0 7
(OpAmp2+, GPIO) P0[4] 8
(OpAmp2-, GPIO) P0[5] 9
(IDAC0, GPIO) P0[6] 10
(IDAC2, GPIO) P0[7] 11
Vccd 12
Vssd 13
Vddd 14
(TRACECLK, GPIO) P2[3] 15
(TRACEDATA[0], GPIO) P2[4] 16
Vddio2 17
(TRACEDATA[1], GPIO) P2[5] 18
(TRACEDATA[2], GPIO) P2[6] 19
(TRACEDATA[3], GPIO) P2[7] 20
Vssb 21
Ind 22
Vboost 23
Vbat 24
48 Vdda
47
Lines show 46
Vddio to I/O
supply
45
association 44
43
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
42 P12[0] (SIO, I2C1: SCL)
41 Vddio3
40 P15[1] (GPIO, MHz XTAL: Xi)
39 P15[0] (GPIO, MHz XTAL: Xo)
38 Vccd
SSOP
37 Vssd
36 Vddd
35 P15[7] (USBIO, D-, SWDCK) [2]
[2]
34 P15[6] (USBIO, D+, SWDIO)
33 P1[7] (GPIO)
32 P1[6] (GPIO)
31 Vddio1
30 P1[5] (GPIO, nTRST)
29 P1[4] (GPIO, TDI)
28 P1[3] (GPIO, TDO, SWV)
27 P1[2] (GPIO, configurable XRES)
26 P1[1] (GPIO, TCK, SWDCK)
25 P1[0] (GPIO, TMS, SWDIO)
Figure 2-2. 68-Pin QFN Part Pinout[3]
(TRACEDATA[2], GPIO) P2[6] 1
(TRACEDATA[3], GPIO) P2[7] 2
(I2C0: SCL, SIO) P12[4] 3
(I2C0: SDA, SIO) P12[5] 4
Vssb 5
Ind 6
Vboost 7
Vbat 8
Vssd 9
XRES 10
(TMS, SWDIO, GPIO) P1[0] 11
(TCK, SWDCK, GPIO) P1[1] 12
(configurable XRES, GPIO) P1[2] 13
(TDO, SWV, GPIO) P1[3] 14
(TDI, GPIO) P1[4] 15
(nTRST, GPIO) P1[5] 16
Vddio1 17
Lines show Vddio
to IO supply
association
QFN
(Top View)
51 P0[3] (GPIO, OpAmp0-/Extref0)
50 P0[2] (GPIO, OpAmp0+)
49 P0[1] (GPIO, OpAmp0out)
48 P0[0] (GPIO, OpAmp2out)
47 P12[3] (SIO)
46 P12[2] (SIO)
45 Vssd
44 Vdda
43 Vssa
42 Vcca
41 P15[3] (GPIO, kHz XTAL: Xi)
40 P15[2] (GPIO, kHz XTAL: Xo)
39 P12[1] (SIO, I2C1: SDA)
38 P12[0] (SIO, 12C1: SCL)
37 P3[7] (GPIO, OpAmp3out)
36 P3[6] (GPIO, OpAmp1out)
35 Vddio3
Notes
2. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground.
3. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
Document Number: 001-55036 Rev. *A
Page 6 of 93
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