DS28E02P 데이터 시트보기 (PDF) - Maxim Integrated

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DS28E02P

1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation

Maxim Integrated 

ABRIDGED DATA SHEET

1-Wire SHA-1 Authenticated 1Kb

EEPROM with 1.8V Operation

the lower 3 bits of the E/S register (ending offset) always

read 1. This indicates that all the data in the scratchpad

is used for a subsequent copying into main memory or

secret. Bit 5 of the E/S register, called PF or partial byte

flag, is a logic 1 if the number of data bits sent by the

master is not an integer multiple of eight or if the data in

the scratchpad is not valid due to a loss of power. A

valid write to the scratchpad clears the PF bit. Bits 3, 4,

and 6 have no function; they always read 1. The partial

flag supports the master checking the data integrity after

a write command. The highest valued bit of the E/S reg-

ister, called authorization accepted (AA), acts as a flag

to indicate that the data stored in the scratchpad has

already been copied to the target memory address.

Writing data to the scratchpad clears this flag.

Writing with Verification

To write data to the DS28E02, the scratchpad must be

used as intermediate storage. First, the master issues

the Write Scratchpad command, which specifies the

desired target address and the data to be written to the

scratchpad. Note that writes to data memory must be

performed on 8-byte boundaries with the three LSBs of

the target address T[2:0] equal to 000b. Therefore, if

T[2:0] are sent with nonzero values, the device sets

these bits to 0 and uses the modified address as the

target address. The master should always send eight

complete data bytes. After the 8 bytes of data have

been transmitted, the master can elect to receive an

inverted CRC-16 of the Write Scratchpad command,

the address as sent by the master, and the data as sent

by the master. The master can compare the CRC to the

value it has calculated itself to determine if the commu-

nication was successful. After the scratchpad has been

written, the master should always perform a read

scratchpad to verify that the intended data was in fact

written. During a read scratchpad, the DS28E02

repeats the target address TA1 and TA2 and sends the

contents of the E/S register. The partial flag (bit 5 of the

E/S register) is set to 1 if the last data byte the DS28E02

received during a write scratchpad or refresh scratch-

pad command was incomplete, or if there was a loss of

power since data was last written to the scratchpad.

The authorization-accepted (AA) flag (bit 7 of the E/S

register) is normally cleared by a write scratchpad or

refresh scratchpad; therefore, if it is set to 1, it indicates

that the DS28E02 did not understand the proceeding

write (or refresh) scratchpad command. In either of

these cases, the master should rewrite the scratchpad.

After the master receives the E/S register, the scratch-

pad data is received. The descriptions of write scratch-

pad and refresh scratchpad provide clarification of

what changes can occur to the scratchpad data under

certain conditions. An inverted CRC of the read

scratchpad command, target address, E/S register, and

scratchpad data follows the scratchpad data. As with

the write scratchpad command, this CRC can be com-

pared to the value the master has calculated to deter-

mine if the communication was successful. After the

master has verified the data, it can send the copy

scratchpad to copy the scratchpad to memory.

Refer to the full data sheet for more information

on Writing RweitfherVteoritfhiceaftuiollnd. ata sheet.

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