EPC16 데이터 시트보기 (PDF) - Altera Corporation
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EPC16 Datasheet PDF : 36 Pages
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Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
Figure 2–3. Concurrent Configuration of Multiple FPGAs in PS Mode (n = 8)
n
(6)
N.C.
n
(6)
N.C.
n
(6)
N.C.
VCC (1) VCC (1)
MSEL
nCEO
FPGA0
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
(3)
(3)
MSEL
nCEO
FPGA1
GND
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
MSEL
nCEO
FPGA7
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
Enhanced Configuration
Device
WE#C
RP#C
DCLK
DATA0
DATA1
OE (3)
nCS (3)
WE#F
RP#F
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
nINIT_CONF (2)
DATA 7
(1)
VCC
WP#
BYTE# (5)
TM1
VCCW
PORSEL
PGM[2..0]
EXCLK
VCC (1)
(4)
(4)
(4)
TMO
GND
C-A0 (5)
C-A1 (5)
C-A15 (5)
C-A16 (5)
A0-F
A1-F
A15-F
A16-F
N.C.
N.C.
N.C.
N.C.
N.C.
Notes to Figure 2–3:
(1) Connect VCC to the same supply voltage as the configuration device.
(2) The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
(4) For PORSEL, PGM[], and EXCLK pin connections, refer to Table 2–9.
(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15
to F-A15, C-A16 to F-A16, and BYTE# to VCC. Additionally, you must make the following pin connections in both
100-pin PQFP and 88-pin Ultra FineLine BGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to VCC, TM0 to
GND, and WP# to VCC.
(6) Connect the FPGA MSEL[] input pins to select the PS configuration mode. For details, refer to the appropriate
FPGA family chapter in the Configuration Handbook.
Altera Corporation
August 2005
2–11
Configuration Handbook, Volume 2
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