EPC16 데이터 시트보기 (PDF) - Altera Corporation

부품명

상세내역

제조사

EPC16

Enhanced Configuration Devices (EPC4, EPC8 & EPC16)

Altera Corporation 

Functional Description

f

For detailed information on using these schemes to configure your

Altera FPGA, refer to the appropriate FPGA family chapter in the

Configuration Handbook.

Configuration Signals

Table 2–3 lists the configuration signal connections between the enhanced

configuration device and Altera FPGAs.

Table 2–3. Configuration Signals

Enhanced

Configuration

Device Pin

Altera

FPGA Pin

Description

DATA[]

DATA[]

Configuration data transmitted from the

configuration device to the FPGA, which is latched

on the rising edge of DCLK.

DCLK

DCLK

Configuration device generated clock used by the

FPGA to latch configuration data provided on the

DATA[] pins.

nINIT_CONF nCONFIG

Open-drain output from the configuration device

that is used to initiate FPGA reconfiguration using

the initiate configuration (INIT_CONF) JTAG

instruction. This connection is not needed if the

INIT_CONF JTAG instruction is not needed. If

nINIT_CONF is not connected to nCONFIG,

nCONFIG must be tied to VCC either directly or

through a pull-up resistor.

OE

nSTATUS Open-drain bidirectional configuration status

signal, which is driven low by either device during

POR and to signal an error during configuration.

Low pulse on OE resets the enhanced

configuration device controller.

nCS

CONF_DONE Configuration done output signal driven by the

FPGA.

2–6

Configuration Handbook, Volume 2

Altera Corporation

August 2005

Share Link: