EPC16 데이터 시트보기 (PDF) - Altera Corporation
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EPC16 Datasheet PDF : 36 Pages
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Functional Description
Figure 2–2. FPP Configuration
n
(6)
N.C.
Stratix Series
or
APEX II Device
MSEL
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
nCEO
nCE
VCC (1) VCC (1)
Enhanced Configuration
Device
(3)
(3)
WE#C
RP#C
DCLK
WE#F
RP#F
DATA[7..0] A[20..0]
OE (3)
RY/BY#
nCS (3)
nINIT_CONF (2) CE#
OE#
(1) VCC
DQ[15..0]
GND
WP#
BYTE# (5)
TM1
VCCW
PORSEL
PGM[2..0]
VCC (1)
(4)
(4)
TMO
EXCLK
(4)
N.C.
N.C.
N.C.
N.C.
N.C.
GND
C-A0 (5)
C-A1 (5)
C-A15 (5)
C-A16 (5)
A0-F
A1-F
A15-F
A16-F
Notes to Figure 2–2:
(1) The VCC should be connected to the same supply voltage as the configuration device.
(2) The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus® II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
(4) For PORSEL, PGM[], and EXCLK pin connections, refer to Table 2–9.
(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15
to F-A15, C-A16 to F-A16, and BYTE# to VCC. Additionally, you must make the following pin connections in both
100-pin PQFP and 88-pin Ultra FineLine BGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to VCC, TM0 to
GND, and WP# to VCC.
(6) Connect the FPGA MSEL[] input pins to select the FPP configuration mode. For details, refer to the appropriate
FPGA family chapter in the Configuration Handbook.
Multiple FPGAs can be configured using a single enhanced configuration
device in FPP mode. In this mode, multiple Stratix series and/or APEX II
FPGAs are cascaded together in a daisy chain.
2–8
Configuration Handbook, Volume 2
Altera Corporation
August 2005
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