GS1560A(2007) 데이터 시트보기 (PDF) - Gennum -> Semtech
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GS1560A Datasheet PDF : 80 Pages
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GS1560A/GS1561 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type Description
22
23, 24
25
26
27
CD_GND
NC
SDO, SDO
NC
RESET_TRST
JTAG/HOST
CS_TMS
–
–
Analog
–
Non
Synchronous
Non
Synchronous
Synchronous
with
SCLK_TCK
Power
–
Output
–
Input
Input
Input
GS1560A
Ground connection for the serial digital cable driver. Connect to analog
GND.
GS1561
No Connect.
GS1560A
Serial digital loop-through output signal operating at 1.485Gb/s,
1.485/1.001Gb/s, or 270Mb/s.
The slew rate of these outputs is automatically controlled to meet SMPTE
292M and 259M specifications according to the setting of the SD/HD pin.
GS1561
No Connect.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and to
reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default conditions
and all input and output signals become high impedance, including the
serial digital outputs SDO and SDO.
Must be set HIGH for normal device operation.
NOTE: When in slave mode, reset the device after the SD/HD input has
been initially configured, and after each subsequent SD/HD data rate
change.
JTAG Test Mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured as GSPI pins for normal host interface operation.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip Select / Test Mode Select
Host Mode (JTAG/HOST = LOW)
CS_TMS operates as the host interface chip select, CS, and is active
LOW.
JTAG Test Mode (JTAG/HOST = HIGH)
CS_TMS operates as the JTAG test mode select, TMS, and is active
HIGH.
NOTE: If the host interface is not being used, tie this pin HIGH.
27360 - 10 January 2007
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