GS71116AJ 데이터 시트보기 (PDF) - Unspecified
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GS71116AJ Datasheet PDF : 15 Pages
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TSOP-II 64K x 16-Pin Configuration
A4
A3
A2
A1
A0
CE
DQ1
DQ2
DQ3
DQ4
VDD
VSS
DQ5
DQ6
DQ7
DQ8
WE
A15
A14
A13
A12
NC
Block Diagram
Top View
1
2
3
4
Top view
5
6
7
8
9
10
11
44-pin
12
13
TSOP II
14
15
16
17
18
19
20
21
22
44
A5
43
A6
42
A7
41
OE
40
UB
39
LB
38
DQ16
37
DQ15
36
DQ14
35
DQ13
34
33
32
VSS
VDD
DQ12
31
DQ11
30
DQ10
29
DQ9
28
NC
27
A8
26
A9
25
A10
24
A11
23
NC
Package TP
A0
Row
Decoder
Address
Input
Buffer
A15
CE
WE
OE
Control
UB _____
LB _____
Memory Array
Column
Decoder
I/O Buffer
DQ1 DQ16
GS71116ATP/J/U
Rev: 1.04a 10/2002
2/15
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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