HD74LS107AFPEL 데이터 시트보기 (PDF) - Renesas Electronics

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HD74LS107AFPEL

Dual J-K Negative-edge-triggeredFlip-Flops (with Clear)

Renesas Electronics 

HD74LS107A

Block Diagram (1/2)

Q

Q

Clear

K

J

Clock

Absolute Maximum Ratings

Item

Symbol

Ratings

Supply voltage

VCC

7

Input voltage

VIN

7

Power dissipation

PT

400

Storage temperature

Tstg

–65 to +150

Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.

Recommended Operating Conditions

Item

Supply voltage

Output current

Operating temperature

Clock frequency

Pulse width

Clock High

Clear Low

Setup time

“H” Data

“L” Data

Hold time

Symbol

VCC

IOH

IOL

Topr

fclock

tw

tsu

th

Min

4.75

—

—

–20

0

20

25

20↓

20↓

0↓

Typ

5.00

—

—

25

—

—

—

—

—

—

Max

5.25

–400

8

75

30

—

—

—

—

—

Unit

V

V

mW

°C

Unit

V

µA

mA

°C

MHz

ns

ns

ns

ns

ns

Rev.3.00, Jul.13.2005, page 2 of 6

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