HI2301
Pin Descriptions (Continued)
PIN NO.
4
SYMBOL
SEL
EQUIVALENT CIRCUIT
AVDD
5
CE
19
TEST
6
CLE
18
20
8
9 to 16
CLK
CLP
DVSS
D7 to D0
4
5
19
AVSSDVSS
AVDD
6
18
20
AVSS CE
DI
17
DVDD
21
ADV
22
ADV
24
VREF
AVDD
CE
21
AVSS
AVDD
22
AVSS
AVDD
24
AVSS
DESCRIPTION
Switches the input of the 3x amplifier. When
SEL is at Low level, VIN1 is selected. When
SEL is at High level, VIN2 is selected.
Standby function ON/OFF selector. In stand-
by state when High.
Fix to VSS for normal use.
When CLE = Low: Clamp function is enabled.
When CLE = High: Clamp function is disabled,
and only the normal A/D converter function is
enabled.
Clock Input.
Inputs the clamp pulse to Pin 20 (CLP).
Clamps the High interval signal voltage.
Digital GND.
D7 (MSB) to D0 (LSB) output. Outputs Low
level in standby. In operation, the phase of D7
to D0 output is inverted against the phase of
ADIN.
5V or 3.3V
Short Pins 21 and 22, and connect 0.1µF
external capacitor.
Clamp reference voltage input. Clamps so
that the reference voltage and the clamp inter-
val ADIN input signal are equal. The reference
voltage is more than 0.5V.
4-3