HMP8116CN 데이터 시트보기 (PDF) - Intersil
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HMP8116CN Datasheet PDF : 43 Pages
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HMP8116
field state. When field information cannot be determined its state at the beginning of each field. FIELD changes state
from the input video source, the FIELD output pin alternates 5±1 CLK2 cycles before the the leading edge of VSYNC.
NTSC(M)
LINE #
524
525
1
2
3
4
5
6
7
8
9
10
PAL(M)
521
522
523
524
525
1
2
3
4
5
6
7
LINE #
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘EVEN’ FIELD
‘ODD’ FIELD
NOTE:
3. The trailing edge of VSYNC is 5±1 clocks after the trailing edge of HSYNC to be VMI compatible and to indicate a transition to an odd field.
FIGURE 4. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION
NTSC(M)
LINE #
262
263
264
265
266
267
268
269
270
271
272
273
PAL(M)
259
260
261
262
263
264
265
266
267
268
269
270
LINE #
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘ODD’ FIELD
‘EVEN’ FIELD
NOTE:
4. The trailing edge of VSYNC is 5±1 clocks after the leading edge of HSYNC to be VMI compatible and to indicate a transition to an even field.
FIGURE 5. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN ODD TO EVEN FIELD TRANSITION
LINE #
621
622
623
624
625
1
2
3
4
5
6
7
VIDEO
INPUT
HSYNC
VSYNC
FIELD
‘EVEN’ FIELD
‘ODD’ FIELD
NOTE:
5. The trailing edge of VSYNC is 5±1 clocks after the trailing edge of HSYNC is to be VMI compatible and to indicate a transition to an odd field.
FIGURE 6. PAL(B,D,G,H,I,N,NC) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION
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