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HSP50214BVC

Programmable Downconverter

Intersil 

HSP50214B

EN EXT TIMING NCO SYNC †

SYNCIN2

SYNC

TIMING PHASE STROBE †

TIMING NCO

PHASE OFFSET †

5

8+

PHASE

ACCUMULATOR

REG

+

FILTER PHASE

SELECT

CARRY OUT = RUN

FILTER STROBE

0

MUX

CLEAR

PHASE

ACC †

ENABLE SOF †

MUX

32

SOF

0

REG

SOFSYNC SYNC

32

SCF

REG

REG

TIMING NCO

PH ACC

LOAD ON

UPDATE†

SYNC

TIMING FREQ

STROBE †

SOF SHIFT REG

NUMBER OF SOF BITS †

TIMING NCO CENTER

FREQUENCY †

† Controlled via microprocessor interface.

FIGURE 26. TIMING NCO BLOCK DIAGRAM

The programmable parameters for the Timing NCO include

an Enable External Timing NCO Sync (Control Word 11, Bit

5), the serial word width, Number of Offset Frequency Bits

(Control Word 11, Bits 3-4), an Enable Offset Frequency

control (Control Word 11, Bit 2), a Clear NCO Accumulator

control (Control Word 11, Bit 1), a Timing NCO Phase

Accumulator Load On Update control (Control Word 11, Bit

0), the Timing NCO Center Frequency (Control Word 12), a

Timing Phase Offset (Control Word 13, Bits 0-7), a Timing

Frequency Strobe (Control Word 14) and a Timing Phase

Strobe (Control Word 15). Refer to the Carrier Synthesizer

Mixer Section for a detailed discussion of the serial interface

for the Timing NCO offset frequency word.

A timing error detector is provided for measuring the phase

difference between the timing NCO and a external clock input,

REFCLK. Timing Error is generated by comparing the values

of two programmable counters. One counter is clocked with

the Timing NCO carry out and the other is clocked by the

REFCLK. The 12-bit NCO Divide parameter is set in Control

Word 18, Bits 16-27. The NCO Divide parameter is the

preload to the counter that is clocked by the Timing NCO carry

out. The 12-bit Reference Divide parameter is set in Control

Word 18, Bits 0-11, and is the preload for the counter that is

clocked by the Reference clock. Figure 26 details the block

diagram of the timing error generation circuit. The 16-bits of

timing error are available both as a PDC serial output and as a

processor read parameter. See the Processor Read Section

for more details on accessing this value.

TIMING

NCO

ACC.

NCO DIVIDE†

(NCO DIVIDE)/2†

REFCLK

12

PROGRAMMABLE

DIVIDER

4

REFERENCE

DIVIDE †

EN

PROGRAMMABLE

DIVIDER

-

TE(15:0)

+

† Controlled via microprocessor interface.

FIGURE 27. TIMING ERROR GENERATION

Figure 27A illustrates an application where the Timing Error

Generator is used to lock the receiver samples with a

transmit data rate. In this example, the receive samples are

at four times the transmit data rate. An external loop filter is

required, whose frequency error output is fed into the Timing

NCO. This allows the loop to track out the long term drift

between the receive sample rate and the transmit data clock.

LOOP

FILTER

μP

TIMING

NCO

ACC.

CLKIN/RT

NCO DIVIDE = 4N†

PROGRAMMABLE

DIVIDER

(NCO DIVIDE)/2†

-

12

+

4

TE(15:0)

Tx DATA CLK

(REFCLK)

REFERENCE

DIVIDE = N †

EN

PROGRAMMABLE

DIVIDER

TO Tx BLOCK

(MODULATOR)

RT = TOTAL DECIMATION (CIC, HB FILTERS AND FIR)

† Controlled via microprocessor interface.

FIGURE 27A. TIMING ERROR APPLICATION

29

FN4450.4

May 1, 2007

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