HT82V842-48LQFP-A 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT82V842-48LQFP-A

CCD CDS/PGA/10b-20M-ADC

Holtek Semiconductor 

AD Conversion Timing (at ADIN (ADC) Input Mode 1 Register D5=1)

ADCK

A D C In p u t

F a llin g E d g e

N +1

N

O U TC K

S a m p lin g P o in t

D ig ita l O u tp u t

N -6

N -5

N +4

tD L

N -2

ADC Direct Input Chart

HT82V842

0 .7 A V D D

0 .3 A V D D

N +5

N +6

0 .7 A V D D

0 .3 A V D D

N -1

N

ADCK

R is in g E d g e

N +1

N

A D C K In p u t

S a m p lin g P o in t

ADCK Inversion Chart

ADCK

tH O L D C

O U TC K

tS U P O C

OUTCK Timing Chart

These figures are shown when the Mode 1 D8 bit is set to ²1², and an external clock is input to the OUTCK pin. When

setting D8 bit to ²0², the ADCK is used as OUTCK.

Note:

At default condition in ADIN mode, data are sampled at the falling edge of the ADCK clock, and are output at

the rising edge of the OUTCK clock. Set the ADCK polarity register to ²1² when the data are sampled and are

output at the falling edge of the ADCK clock.

The diagram on the upper portion of this page shows the default timing and the lower left figure shows the in-

verted timing.

Delay from data sampling to data output

ADCK normal: At Mode 1 register D6=0; 5.5 clk delay

ADCK inversion: At Mode 1 register D6=1; 6.0 clk delay

In ADIN input mode, the above mentioned register setting is available.

At ADIN (PGA) input Mode 1 register D5=0 and D4=1, digital data output is delayed by 2 clks.

ADCK Clock Waveform

tH

0 .7 V D D

Rev. 1.00

0 .3 V D D

tR

tF

tL

tC Y C

12

July 15, 2004

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