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HX6356KBNC

32K x 8 STATIC RAM-SOI

Unspecified 

Aerospace Electronics

32K x 8 STATIC RAM—SOI

HX6356

FEATURES

RADIATION

OTHER

• Fabricated with RICMOS™ IV Silicon on Insulator (SOI)

0.75

µm

Process

(L

eff

=

0.6

µm)

• Total Dose Hardness through 1x106 rad(SiO2)

• Neutron Hardness through 1x1014 cm-2

• Dynamic and Static Transient Upset Hardness

through 1x1011 rad(Si)/s

• Listed On SMD# 5962-95845

• Fast Read/Write Cycle Times

≤ 17 ns (Typical)

≤ 25 ns (-55 to 125°C)

• Typical Operating power < 15 mW/MHz

• Asynchronous Operation

• Dose Rate Survivability through 1x1012 rad(Si)/s

• CMOS or TTL Compatible I/O

• Soft Error Rate of <1x10-10 upsets/bit-day

in Geosynchronous Orbit

• Latchup Free

• Single 5 V ± 10% Power Supply

• Packaging Options

- 36-Lead CFP—Bottom Braze (0.630 in. x 0.650 in.)

- 36-Lead CFP—Top Braze (0.630 in. x 0.650 in.)

GENERAL DESCRIPTION

The 32K x 8 Radiation Hardened Static RAM is a high

performance 32,768 word x 8-bit static random access

memory with industry-standard functionality. It is fabricated

with Honeywell’s radiation hardened technology, and is

designed for use in systems operating in harsh, transient

radiation environments. The RAM operates over the full

military temperature range and requires only a single 5 V ±

10% power supply. The RAM is available with either TTL or

CMOS compatible I/O. Power consumption is typically less

than 15 mW/MHz in operation, and less than 5 mW when

de-selected. The RAM read operation is fully asynchro-

nous, with an associated typical access time of 14 ns at 5V.

Honeywell’s enhanced SOI RICMOS™IV (Radiation Insen-

sitive CMOS) technology is radiation hardened through the

use of advanced and proprietary design, layout and pro-

cess hardening techniques. The RICMOS™ IV process is a

5-volt, SIMOX CMOS technology with a 150 Å gate oxide

and a minimum drawn feature size of 0.75 µm (0.6 µm

effective gate length—Leff). Additional features include

tungsten via plugs, Honeywell’s proprietary SHARP pla-

narization process, and a lightly doped drain (LDD) struc-

ture for improved short channel reliability. A 7 transistor

(7T) memory cell is used for superior single event upset

hardening, while three layer metal power bussing and the

low collection volume SIMOX substrate provide improved

dose rate hardening.

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