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ICS8312I 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS8312I
ICST
Integrated Circuit Systems 
ICS8312I Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
Integrated
Circuit
Systems, Inc.
ICS8312I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
fMAX
tpLH
tsk(o)
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f 250MHz
tsk(pp) Part-to-Part Skew; NOTE 3, 5
tR/ tF
Output Rise Time; NOTE 4
odc
Output Duty Cycle
20% to 80%
f 150MHz
All parameters measured at fMAX unless noted otherwise.
See Table 5C listed below for Notes 1 through 5.
Minimum
1.2
175
45
Typical
2.0
Maximum Units
250
MHz
2.7
ns
150
ps
850
ps
800
ps
55
%
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
fMAX
tpLH
tsk(o)
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f 250MHz
tsk(pp) Part-to-Part Skew; NOTE 3, 5
tR/ tF
Output Rise Time; NOTE 4
odc
Output Duty Cycle
20% to 80%
f 150MHz
All parameters measured at fMAX unless noted otherwise.
See Table 5C listed below for Notes 1 through
Minimum
1.25
200
45
Typical
2.4
Maximum Units
250
MHz
3.5
ns
155
ps
1.1
ns
800
ps
55
%
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
tsk(o)
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f 200MHz
200
MHz
1.6
3.3
4.9
ns
160
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
2.4
ns
t /t
Output Rise Time; NOTE 4
RF
odc
Output Duty Cycle
20% to 80%
175
f 100MHz
45
875
ps
55
%
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8312AYI
http://www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 23, 2003

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