IDT49FCT805BT 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT49FCT805BT

FAST CMOS BUFFER/CLOCK DRIVER

Integrated Device Technology 

IDT49FCT805BT/CT

FAST CMOS BUFFER/CLOCK DRIVER

TEST CIRCUITS AND WAVEFORMS

VCC

7V

V IN

Pulse

Generator

500Ω

VOUT

D .U .T .

50pF

RT

500Ω

CL

Test Circuits for All Outputs

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCH POSITION

Test

Disable LOW

Enable LOW

Disable HIGH

Enable HIGH

Switch

Closed

GND

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

IN P U T

OUTPUT

IN P U T

OUTPUT

tPLH

tPHL

tR

tF

Package Delay

3V

1.5V

0V

VOH

2.0V

1.5V

0.8V

VOL

tPLH

tPHL

tSK(p) = tPHL - tPLH

Pulse Skew - tSK(P)

3V

1.5V

0V

VOH

1.5V

VOL

CONTROL

IN P U T

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

ENABLE

tPZL

SW IT CH

CLOSED

tPZH

3.5V

1.5V

SW ITCH

OPEN

1.5V

0V

DISABLE

tPLZ

3V

1.5V

0V

tP H Z

3.5V

0.3V VOL

0.3V VOH

0V

Enable and Disable Times

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

IN P U T

OUTPUT 1

OUTPUT 2

tPLH1

tPLH1

tSK(o)

tSK(o)

tPLH2

tP H L 2

tSK(o) = tPLH2 - tPLH1 or tPHL2 - tPHL1

Output Skew

3V

1.5V

0V

VOH

1.5V

VOL

VOH

1.5V

VOL

INPUT

tPLH1

tPHL1

PACKAGE 1

OUTPUT

PACKAGE 2

OUTPUT

tSK(pp)

tS K (p p )

tPLH2

tP H L 2

tSK(pp) = tPLH2 - tPLH1 or tPHL2 - tPHL1

Part-to-Part Skew - tSK(PP)

3V

1.5V

0V

VOH

1.5V

VOL

VOH

1.5V

VOL

NOTE:

1. Package 1 and Package 2 are same device type and speed grade.

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