IDT70121 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT70121

HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

Integrated Device Technology 

IDT70121/IDT70125

High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt

Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY(1,2,3)

tWC

ADDR 'A'

MATCH

tWP

R/W'A'

DATAIN'A'

tAPS (1)

tDW

tDH

VALID

ADDR'B'

MATCH

tBDA

tBDD

BUSY'B'

tWDD

DATAOUT 'B'

tDDD(4)

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT70125).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".

VALID

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Timing Waveform of Write with BUSY(3)

tWP

R/W"A"

tWB

BUSY"B"

tWH (1)

R/W"B"

(2)

,

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NOTES:

1. tWH must be met for both BUSY input (slave) and output (master).

2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.

3. All timing is the same for left and right ports. Port"A" may be either left or right port. Port "B" is the opposite from port "A".

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

ADDR"A and B" (1)

ADDRESSES MATCH

CE"A"

CE"B"

BUSY"B"

tAPS(2)

tBAC

tBDC

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted

(70121 only).

11

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