IDT71V3559S 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT71V3559S
Integrated Device Technology
IDT71V3559S Datasheet PDF : 28 Pages
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IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used (1)
Cycle
Address
R/W ADV/LD CE1(2) CEN BWx
OE
I/O(3) Comments
n
X
X
L
H
L
X
X
? Deselected.
n+1
X
X
L
H
L
X
X
Z Deselected.
n+2
A0
H
L
L
L
X
X
Z Address A0 and Control meet setup.
n+3
X
X
L
H
L
X
L
Q0 Address A0 read out, Deselected.
n+4
A1
H
L
L
L
X
X
Z Address A1 and Control meet setup.
n+5
X
X
L
H
L
X
L
Q1 Address A1 read out, Deselected.
n+6
X
X
L
H
L
X
X
Z Deselected.
n+7
A2
H
L
L
L
X
X
Z Address A2 and Control meet setup.
n+8
X
X
L
H
L
X
L
Q2 Address A2 read out, Deselected.
n+9
X
X
L
H
L
X
X
Z Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
5282 tbl 19
Write Operation with Chip Enable Used (1)
Cycle Address R/W ADV/LD CE(2) CEN BWx OE
n
X
X
L
H
L
X
X
n+1
X
X
L
H
L
X
X
n+2
A0
L
L
L
L
L
X
n+3
X
X
L
H
L
X
X
n+4
A1
L
L
L
L
L
X
n+5
X
X
L
H
L
X
X
n+6
X
X
L
H
L
X
X
n+7
A2
L
L
L
L
L
X
n+8
X
X
L
H
L
X
X
n+9
X
X
L
H
L
X
X
I/O Comments
? Deselected.
Z Deselected.
Z Address A0 and Control meet setup
D0 Data D0 Write In, Deselected.
Z Address A1 and Control meet setup
D1 Data D1 Write In, Deselected.
Z Deselected.
Z Address A2 and Control meet setup
D2 Data D2 Write In, Deselected.
Z Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
5282 tbl 20
6.1442
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