IDT723611(1999) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT723611
(Rev.:1999)

CMOS SyncFIFO™ 64 x 36

Integrated Device Technology 

CMOS SyncFIFOTM

64 x 36

IDT723611

FEATURES:

♦ Free-running CLKA and CLKB may be asynchronous or

coincident (permits simultaneous reading and writing of data on

a single clock edge)

♦ 64 x 36 storage capacity

♦ Synchronous data buffering from Port A to Port B

♦ Mailbox bypass register in each direction

♦ Programmable Almost-Full ( AF ) and Almost-Empty ( AE ) flags

♦ Microprocessor Interface Control Logic

♦ Full Flag ( FF ) and Almost-Full ( AF ) flags synchronized by CLKA

♦ Empty Flag ( EF ) and Almost-Empty ( AE ) flags synchronized by

CLKB

♦ Passive parity checking on each Port

♦ Parity Generation can be selected for each Port

♦ Supports clock frequencies up to 67MHz

♦ Fast access times of 10ns

♦ Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving

120-pin Thin Quad Flatpack (PF)

♦ Industrial temperature range (–40°C to +85°C) is available

DESCRIPTION:

The IDT723611 is a monolithic, high-speed, low-power, CMOS Syn-

chronous (clocked) FIFO memory which supports clock frequencies up to

67MHz and has read access times as fast as 10ns. The 64 x 36 dual-port FIFO

buffers data from Port A to Port B. The FIFO has flags to indicate empty and

full conditions, and two programmable flags, Almost-Full (AF) and Almost-Empty

(AE), to indicate when a selected number of words is stored in memory.

Communication between each port can take place through two 36-bit mailbox

registers. Each mailbox register has a flag to signal when new mail has been

stored. Parity is checked passively on each port and may be ignored if not

desired. Parity generation can be selected for data read from each port. Two

or more devices may be used in parallel to create wider data paths.

FUNCTIONAL BLOCK DIAGRAM

CLKA

CSA

W/RA

ENA

MBA

Port-A

Control

Logic

RST

ODD/

EVEN

Reset

Logic

36

A0 - A35

FF

AF

FIFO

FS0

FS1

Mail 1

Register

RAM

ARRAY

64 x 36

Write Read

Pointer Pointer

Status Flag

Logic

Programmable

Flag Offset

Registers

Parity

Gen/Check

PGA

PEFA

MBF2

Parity

Gen/Check

Mail 2

Register

1

© 1999 Integrated Device Technology, Inc.

MBF1

PEFB

PGB

B0 - B35

EF

AE

Port-B

Control

Logic

CLKB

CSB

W/RB

ENB

MBB

3024 drw 01

SEPTEMBER 1999

DSC-3024/-

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