IDT723611L20PF 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT723611L20PF

CMOS SyncFIFO 64 x 36

Integrated Device Technology 

IDT723611 CMOS SyncFIFO™

64 x 36

CLKB

CSB

W/RB

MBB

ENB

tCLK

tCLKH

tCLKL

LOW

LOW

LOW

tENS2

tENH2

COMMERCIAL TEMPERATURE RANGES

EFB

B0 -B35

CLKA

FF

HIGH

tA

Previous Word in FIFO Output Register

tSKEW1(1)

Next Word From FIFO

tCLK

tCLKH

tCLKL

1

FIFO Full

2

tWFF

tWFF

CSA

LOW

WRA

MBA

HIGH

tENS3

tENH3

tENS2

tENH2

ENA

tDS

tDH

A0 - A35

To FIFO

3024 drw 08

Note:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between

the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.

Figure 5. FF Flag Timing and First Available Write when the FIFO is Full

CLKA

ENA

CLKB

AE

tENS2

tENH2

(1)

tSKEW2

1

X Word in FIFO

2

tPAE

(X+1) Words in FIFO

tENS2

tPAE

tENH2

ENB

3024 drw 09

Notes:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next

CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may

transition HIGH one CLKB cycle later than shown.

2. FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).

Figure 6. Timing for AE when the FIFO is Almost Empty

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