IDT723611L20PF 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT723611L20PF Datasheet PDF : 20 Pages
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IDT723611 CMOS SyncFIFO™
64 x 36
TYPICAL CHARACTERISTICS
COMMERCIAL TEMPERATURE RANGES
SUPPLY CURRENT
vs
CLOCK FREQUENCY
400
350
f data = 1/2 f s
TA = 25° C
300
C L = 0 pF
250
VCC = 5.0 V
VCC = 5.5 V
200
VCC = 4.5 V
150
100
50
0
0
10
20
30
40
50
60
70
80
f clock – Clock Frequency – MHz
Figure 14.
3024 drw 17
CALCULATING POWER DISSIPATION
The ICC(f) data for the graph was taken while simultaneously reading and writing the FIFO on the IDT723611 with
CLKA and CLKB operating at frequency fS. All data inputs and data outputs change state during each clock cycle to
consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load.
Once the capacitance load per data-output channel is known, the power dissipation can be calculated with the equation
below.
With ICC(f) taken from FIgure 14, the maximum power dissipation (PT) of the IDT723611 may be calculated by:
PT = VCC x ICC(f) + ∑(CL x VOH - VOL)2 X fO)
where:
CL =
fO =
output capacitance load
switching frequency of an output
VOH =
output high-level voltage
VOL =
output low-level voltage
When no read or writes are occurring on the IDT723611, the power dissipated by a single clock (CLKA or CLKB) input
running at frequency fS is calculated by:
PT = VCC x fS x 0.290 mA/MHz
18
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