MCM69R738A 데이터 시트보기 (PDF) - Motorola => Freescale
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MCM69R738A Datasheet PDF : 20 Pages
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AC OPERATING CONDITIONS AND CHARACTERISTICS
(0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V
Clock Input Timing Reference Level . . . . . . Differential Cross–Point
Clock Input Pulse Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 V to 2.1 V
RθJA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
READ/WRITE CYCLE TIMING (See Note 1)
MCM69R738A–5 MCM69R738A–6 MCM69R738A–7 MCM69R738A–8
MCM69R820A–5 MCM69R820A–6 MCM69R820A–7 MCM69R820A–8
Parameter
Symbol Min
Max
Min
Max
Min
Max
Min
Max Unit Note
s
Cycle Time
tKHKH
5
—
6
—
7
—
8
—
ns
Clock High Pulse Width
tKHKL
2
—
2.4
—
2.8
—
3.2
—
ns
Clock Low Pulse Width
tKLKH
2
—
2.4
—
2.8
—
3.2
—
ns
Clock High to Output Low–Z tKHQX1
1
—
1
—
1
—
1
—
ns 2, 3
Clock High to Output Valid
tKHQV
—
2.5
—
3
—
3.5
—
4
ns
Clock High to Output Hold
tKHQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
2
Clock High to Output High–Z tKHQZ
—
2.5
—
3
0
3.5
0
4
ns 2, 3
Output Enable Low to Output tGLQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Low–Z
Output Enable Low to Output tGLQV
—
2.5
—
3
—
3.5
—
4
ns
Valid
Output Enable to Output Hold tGHQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Output Enable High to Output tGHQZ
—
2.5
—
3
—
3.5
—
4
ns 2, 3
High–Z
Setup Times:
Address tAVKH
0.5
—
0.5
—
0.5
—
0.5
—
ns
Data In tDVKH
Chip Select tSVKH
Write Enable tWVKH
Hold Times:
Address tKHAX
1
—
1
—
1
—
1
—
ns
Data In tKHDX
Chip Select tKHSX
Write Enable tKHWX
NOTES:
1. In no case may control input signals (e.g., SS) be operated with pulse widths less than the minimum clock input pulse width specifications
(e.g., tKHKL) or at frequencies that exceed the applied K clock frequency.
2. This parameter is sampled and not 100% tested.
3. Measured at ± 200 mV from steady state.
DEVICE
UNDER
TEST
VDDQ/2
50 Ω
50 Ω
TIMING LIMITS
The table of timing values shows either a minimum or
a maximum limit for each parameter. Input require-
ments are specified from the external system point of
view. Thus, address setup time is shown as a minimum
since the system must supply at least that much time
(even though most devices do not require it). On the oth-
er hand, responses from the memory are specified from
the device point of view. Thus, the access time is shown
as a maximum since the device never provides data lat-
er than that time.
Figure 1. AC Test Load
MOTOROLA FAST SRAM
MCM69R738A•MCM69R820A
7
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