ISL90810WIU8(2005) 데이터 시트보기 (PDF) - Intersil
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ISL90810WIU8 Datasheet PDF : 11 Pages
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ISL90810
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 1) MAX UNITS
tDCP (Note 13) DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to
wiper change
1
µs
Vpor
VCCRamp
tD (Note 13)
Power-On Recall Voltage
VCC Ramp Rate
Power-Up Delay
Minimum VCC at which memory recall occurs
1.8
0.2
VCC above Vpor,
recall completed,
to DCP
and I2C
Initial Value
Interface in
Register
standby state
2.6
V
V/ms
3
ms
SERIAL INTERFACE SPECIFICATIONS
VIL
SDA, and SCL Input Buffer LOW
Voltage
-0.3
0.3*VCC V
VIH
SDA, and SCL Input Buffer HIGH
Voltage
0.7*VCC
VCC+0.3 V
Hysteresis SDA and SCL Input Buffer Hysteresis
(Note 13)
VOL (Note 13) SDA Output Buffer LOW Voltage,
Sinking 4mA
0.05*
VCC
0
V
0.4
V
Cpin (Note 13) SDA, and SCL Pin Capacitance
10
pF
fSCL
tIN (Note 13)
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
400
kHz
50
ns
tAA (Note 13) SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until SDA
Valid
exits the 30% to 70% of VCC window.
tBUF (Note 13) Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of VCC during
the following START condition.
1300
900
ns
ns
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tHD:STO
tDH (Note 13)
tR (Note 13)
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
600
crossing 70% of VCC.
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to 600
SCL falling edge crossing 70% of VCC.
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
100
window, to SCL rising edge crossing 30% of VCC
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to
0
SDA entering the 30% to 70% of VCC window.
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to 600
SDA rising edge crossing 30% of VCC.
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge. Both 600
or Volatile Only Write
crossing 70% of VCC.
Output Data Hold Time
From SCL falling edge crossing 30% of VCC, until 0
SDA enters the 30% to 70% of VCC window.
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
ns
ns
ns
ns
ns
ns
ns
ns
ns
250
ns
tF (Note 13) SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb (Note 13) Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
Rpu (Note 13) SDA and SCL Bus Pull-Up Resistor Maximum is determined by tR and tF.
1
kΩ
Off-Chip
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
4
FN8234.1
October 13, 2005
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