ISL97676 데이터 시트보기 (PDF) - Intersil

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ISL97676

6-Channel LED Driver with Phase Shift Control

Intersil 

ISL97676

TABLE 3. PROTECTIONS TABLE (Continued)

CASE FAILURE MODE

DETECTION MODE

GOOD CHANNELS

FAILED CHANNEL ACTION

ACTION

VOUT

REGULATED

BY

4 FB1 Open Circuit Upper OTP not triggered VOUT will ramp to OVP. FB1 FB2 through FB6

with infinite

and FB1 < 4V

will time-out after 6 PWM Normal

resistance

cycles and switch off. VOUT

will drop to normal level.

Highest VF of

FB2 through FB6

5 FB1 LED Open

Circuit but has

paralleled Zener

Upper OTP not triggered

and FB1 < 4V

FB1 remains ON and has

highest VF, thus VOUT

increases.

FB2 through FB6 ON,

Q2 through Q6 burn

power

VF of FB1

6 FB1 LED Open

Circuit but has

paralleled Zener

Upper OTP triggered but

FB1 < 4V

All channels go off until chip

cooled and then comes back

on with current reduced to

76%. Subsequent OTP

triggers will reduce Iout

further

Same as FB1

VF of FB1

7 FB1 LED Open

Circuit but has

paralleled Zener

Upper OTP not triggered

but FBx > 4V

FB1 remains ON and has

highest VF, thus VOUT

increases.

VOUT increases, then

FB-X switches OFF after

6 PWM cycles. This is an

unwanted shut off and

can be prevented by

setting OVP at an

appropriate level.

VF of FB1

8 Channel-to-Channel Lower OTP triggered but Any channel at below the target current will fault out Highest VF of

ΔVF too high

FBx < 4V

after 6 PWM cycles.

FB1 through FB6

Remaining channels driven with normal current.

9 Channel-to-Channel Upper OTP triggered but All channels go off until chip cooled and then comes Highest VF of

ΔVF too high

FBx < 4V

back on with current reduced to 76%. Subsequent OTP FB1 through FB6

triggers will reduce Iout further

10 Output LED stack VOUT > VOVP

voltage too high

Any channel that is below the target current will time- Highest VF of

out after 6 PWM cycles, and Vout will return to the FB1 through FB6

normal regualtion voltage required for other channels.

11 VOUT/LX shorted to LX current and timing are The chip is permanently shutdown 31mS after

GND at start-up or monitored.

powerup if Vout/Lx is shorted to GND.

VOUT shorted in

operation

OVP pins monitored for

excursions below 20% of

OVP threshold.

Components Selections

According to the inductor Voltage-Second Balance

principle, the change of inductor current during the

switching regulator On-time is equal to the change of

inductor current during the switching regulator Off-time.

Since the voltage across an inductor is:

VL = L × ΔIL ⁄ Δt

(EQ. 11)

and ΔIL @ TON = ΔIL @ TOFF, therefore:

(VI – 0 ) ⁄ L × D × tS= (VO – VD – VI) ⁄ L × (1 – D ) × tS

(EQ. 12)

where D is the switching duty cycle defined by the turn-on

time over the switching period. VD is Schottky diode

forward voltage which can be neglected for

approximation.

Rearranging the terms without accounting for VD gives

the boost ratio and duty cycle respectively as:

VO ⁄ VI = 1 ⁄ (1 – D)

(EQ. 13)

D = (VO – VI ) ⁄ VO

(EQ. 14)

17

FN7600.0

March 12, 2010

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