KS8721CL 데이터 시트보기 (PDF) - Micrel
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KS8721CL Datasheet PDF : 33 Pages
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KS8721CL
Pin Description
Pin Number Pin Name
1
MDIO
2
MDC
3
RXD3/
PHYAD
4
RXD2/
PHYAD2
5
RXD1/
PHYAD3
6
RXD0/
PHYAD4
7
VDDIO
8
GND
9
RXDV/
CRSDV/
PCS_LPBK
10
RXC
11
RXER/ISO
12
GND
13
VDDC
14
TXER
15
TXC/
REFCLK
16
TXEN
17
TXD0
18
TXD1
Type(1)
I/O
I
Ipd/O
Ipd/O
Ipd/O
Ipd/O
P
GND
Ipd/O
O
Ipd/O
GND
P
Ipd
I/O
Ipd
Ipd
Ipd
Micrel, Inc.
Pin Function
Management Independent Interface (MII) Data I/O. This pin requires an external
4.7K pull-up resistor.
MII Clock Input. This pin is synchronous to the MDIO.
MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
RXD [3..0] is invalid when RXDV is de-asserted.
During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See
“Strapping Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See
“Strapping Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR [3]. See
“Strapping Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR [4]. See
“Strapping Options” section for details.
Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage
regulator. See “Circuit Design Ref. for Power Supply" section for details.
Ground.
MII Receive Data Valid Output.
During reset, the pull-up/pull-down value is latched as PCS_LPBK. See
“Strapping Options” section for details.
MII Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
MII Receive Error Output.
During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See
“Strapping Options” section for details.
Ground.
Digital core 2.5V only power supply. See “Circuit Design Ref. for Power Supply"
section for details.
MII Transmit Error Input.
MII Transmit Clock Output.
Input for crystal or an external 50MHz clock. When REFCLK pin is used for
REF clock interface, pull up XI to VDDPLL 2.5V via 10kΩ resistor and leave
XO pin unconnected.
MII Transmit Enable Input.
MII Transmit Data Input.
MII Transmit Data Input.
Notes:
1. P = Power supply.
GND = Ground.
I = Input.
I/O = Bidirectional.
Ipd = Input w/ internal pull-down.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu = Input w/ internal pull-up.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
O = Output.
M9999-041405
6
April 2005
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