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LNK409 데이터 시트보기 (PDF) - Power Integrations, Inc

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LNK409 Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LNK403-409/413-419
BYPASS (BP)
VOLTAGE
MONITOR (V)
FEEDBACK (FB)
REFERENCE (R)
BYPASS
CAPACITOR
SELECT
SOFT-START
TIMER
1V
3-VT
ILIM
MI
STOP
LOGIC
AUTO-RESTART
COUNTER
JITTER
CLOCK
OSCILLATOR
UV/OV
LINE
SENSE
VBG
FEEDBACK
SENSE
6.4 V
IV
IFB
FBOFF
DCMAX
PFC/CC
CONTROL
REFERENCE
BLOCK
5.9 V
REGULATOR
FAULT
PRESENT
HYSTERETIC
THERMAL
SHUTDOWN
5.9 V
5.0 V
BYPASS PIN
UNDERVOLTAGE
Comparator
FBOFF
DCMAX
OCP
Gate
Driver
SenseFet
LEB
CURRENT LIMIT
COMPARATOR
ILIM
MI
VSENSE
IS
VBG
DRAIN (D)
PI-5431-102610
SOURCE (S)
Figure 3. Functional Block Diagram.
Pin Functional Description
DRAIN (D) Pin:
This pin is the power FET drain connection. It also provides
internal operating current for both start-up and steady-state
operation.
VOLTAGE MONITOR (V) Pin:
This pin interfaces with an external input line peak detector,
consisting of a rectifier, filter capacitor and resistors. The
applied current is used to control stop logic for line under-
voltage (UV), overvoltage (OV), provide feed-forward to control
the output current and the remote ON/OFF function.
SOURCE (S) Pin:
This pin is the power FET source connection. It is also the
ground reference for the BYPASS, FEEDBACK, REFERENCE and
VOLTAGE MONITOR pins.
BYPASS (BP) Pin:
This is the connection point for an external bypass capacitor for
the internally generated 5.9 V supply. This pin also provides
output power selection through choice of the BYPASS pin
capacitor value.
FEEDBACK (FB) Pin:
The FEEDBACK pin is used for output voltage feedback. The
current into the FEEDBACK pin is directly proportional to the
output voltage. The FEEDBACK pin also includes circuitry to
protect against open load and overload output conditions.
REFERENCE (R) Pin:
This pin is connected to an external precision resistor and is
used to configure for dimming (LNK403-409) and non-TRIAC
dimming (LNK413-419) modes of operation.
E Package (eSIP-7C)
(Top View)
Exposed Pad
(Backside) Internally
Connected to
SOURCE Pin
L Package (eSIP-7F)
Exposed Pad
(backside) Internally
Connected to
SOURCE Pin (see
eSIP-7C Package
Drawing)
7D
5S
4 BP
3 FB
2V
1R
135
Lead
from
Bend Outward
Drawing
R FB S
24
V BP
(Refer to eSIP-7F Package
Outline Drawing)
7
D
PI-5432-082411
Figure 4. Pin Configuration.
2
Rev. D 08/11
www.powerint.com

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