LPC47N267(2000) 데이터 시트보기 (PDF) - SMSC -> Microchip
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LPC47N267 Datasheet PDF : 180 Pages
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11.6
11.7
12.0
12.1
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12.8
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24.1
24.2
ECP IMPLEMENTATION STANDARD .................................................................................................................80
PARALLEL PORT FLOPPY DISK CONTROLLER ...................................................................................................88
POWER MANAGEMENT ..............................................................................................................................90
FDC POWER MANAGEMENT...........................................................................................................................90
DSR FROM POWERDOWN..............................................................................................................................90
WAKE UP FROM AUTO POWERDOWN ..............................................................................................................90
REGISTER BEHAVIOR.....................................................................................................................................90
PIN BEHAVIOR ..............................................................................................................................................91
UART POWER MANAGEMENT ........................................................................................................................92
EXIT AUTO POWERDOWN...............................................................................................................................92
PARALLEL PORT ...........................................................................................................................................92
SERIAL IRQ ..................................................................................................................................................93
TIMING DIAGRAMS FOR SER_IRQ CYCLE.......................................................................................................93
ROUTABLE IRQ INPUTS .................................................................................................................................95
PCI CLKRUN SUPPORT ..............................................................................................................................96
OVERVIEW ...................................................................................................................................................96
NCLKRUN FOR SERIAL IRQ .........................................................................................................................96
NCLKRUN FOR LDRQ# ...............................................................................................................................96
USING NCLKRUN ........................................................................................................................................96
X-BUS INTERFACE ......................................................................................................................................98
X-BUS MODES..............................................................................................................................................99
GENERAL PURPOSE I/O ...........................................................................................................................102
GPIO PINS ................................................................................................................................................102
DESCRIPTION..............................................................................................................................................103
GPIO CONTROL .........................................................................................................................................104
GPIO OPERATION ......................................................................................................................................104
GPIO PME AND SMI FUNCTIONALITY...........................................................................................................105
SYSTEM MANAGEMENT INTERRUPT (SMI)............................................................................................106
SMI REGISTERS .........................................................................................................................................106
PME SUPPORT...........................................................................................................................................106
PME REGISTERS ........................................................................................................................................107
RUNTIME REGISTERS...............................................................................................................................107
RUNTIME REGISTERS BLOCK SUMMARY ........................................................................................................107
RUNTIME REGISTERS BLOCK DESCRIPTION ...................................................................................................108
CONFIGURATION ......................................................................................................................................113
CONFIGURATION ACCESS PORTS..................................................................................................................113
CONFIGURATION STATE ...............................................................................................................................113
CONFIGURATION REGISTERS SUMMARY ........................................................................................................114
CONFIGURATION REGISTERS DESCRIPTION ...................................................................................................116
LOGICAL DEVICE BASE I/O ADDRESS AND RANGE ..........................................................................................148
NOTE A. LOGICAL DEVICE IRQ AND DMA OPERATION ...................................................................................150
OPERATIONAL DESCRIPTION .................................................................................................................151
MAXIMUM GUARANTEED RATINGS.................................................................................................................151
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................151
TIMING DIAGRAMS....................................................................................................................................154
PACKAGE OUTLINES................................................................................................................................178
APPENDIX - TEST MODES ........................................................................................................................179
BOARD TEST MODE.....................................................................................................................................179
XNOR-CHAIN TEST MODE ..........................................................................................................................179
SMSC DS – LPC47N267
Page 5
Rev. 10/23/2000
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