LT3501 데이터 시트보기 (PDF) - Linear Technology
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LT3501 Datasheet PDF : 30 Pages
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LT3501
Block Diagram
RT/SYNC
R3
VIN1
INTERNAL
REGULATOR
AND
REFERENCE
3µA
7µA
SHDN
+
1.28V
+
–
SHUTDOWN
COMPARATOR
POR
UNDERVOLTAGE
TSD
OSCILLATOR
AND
AGC
CLK1
CLK2
ONE CHANNEL
DROPOUT
ENHANCEMENT
SLOPE
Σ
COMPENSATION
–
+
S PRE
Q
R
DRIVER
CIRCUITRY
+
0.8V
S
RQ
LOWEST
VOLTAGE
VC CLAMP
3.25mA
POWER GOOD
COMPARATOR
–
+
SS CLAMP
+
+
SOFT-START
80mV
GND
RESET
0.72V
COMPARATOR
SS
VC
C
VIN
BST
SW
IND
VOUT
FB
PGOOD
3501 BD
C
C3
L1
D
D
C
R1
R2
Figure 1. Block Diagram (One of Two Switching Regulators Shown)
The LT3501 is dual-channel, constant-frequency, current
mode buck converter with internal 3A switches. Each
channel is identical with a common shutdown pin, internal
regulator, oscillator, undervoltage detect, thermal shutdown
and power-on reset.
If the SHDN pin is taken below its 1.28V threshold the
LT3501 will be placed in a low quiescent current mode.
In this mode the LT3501 typically draws 9µA from VIN1
and <1µA from VIN2. In shutdown mode the PG is active
with a typical sink capability of 50µA for VIN1 voltage
greater than 2V.
When the SHDN pin is opened or driven above 1.28V,
the internal bias circuits turn on generating an internal
regulated voltage, 0.8VFB, 0.975V RT/SYNC references,
and a POR signal which sets the soft-start latch.
As the RT/SYNC pin reaches its 0.975V regulation point,
the internal oscillator will start generating two clock sig-
nals 180° out of phase for each regulator at a frequency
determined by the resistor from the RT/SYNC pin to ground.
Alternatively, if a synchronization signal is detected by the
LT3501 at the RT/SYNC pin, clock signals 180° out of phase
3501fd
10
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