LT5546 데이터 시트보기 (PDF) - Linear Technology
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LT5546 Datasheet PDF : 12 Pages
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LT5546
APPLICATIO S I FOR ATIO
up recovery from an overload event, which can occur
during the gain settling. The clipping level is approxi-
mately constant over temperature. The first order inte-
grated lowpass filters are used for noise filtering of the
down-converted baseband signals for both the I channel
and the Q channel. These filters are well matched in gain
response. The –3dB corner frequency is typically 17MHz.
The I/Q outputs can drive 2kΩ in parallel with a maximum
capacitive loading of 10pF at 5MHz, from all four pins to
ground. The outputs are internally biased at VCC – 1.19V.
Figure 5 shows the simplified output circuit schematic of
the I channel or Q channel.
The I/Q baseband outputs can be DC-coupled to the inputs
of a baseband chip. For AC-coupled applications with large
capacitors, the STBY pin can be used to pre-bias the
outputs to nominal VCC – 1.19V at much reduced current.
This mode draws only 3.6mA supply current. When the EN
pin is then driven high (>1V), the chip is quickly switched
to normal operating mode, avoiding the introduction of
large charging time constants. Table 2 shows the logic of
the EN pin and STBY pin. In both normal operating mode
and standby mode, the maximum discharging current is
about 300µA, and the maximum charging current is more
than 4mA. In Figure 5 the simplified circuit schematic of
the STBY (or EN) input is shown.
Table 2. The Logic of Different Operating Modes
EN
STBY
Comments
Low
Low
Shutdown Mode
Low
High
Standby Mode
High
Low or High
Normal Operation Mode
VCC
VCC
I CHANNEL (OR
Q CHANNEL):
DIFFERENTIAL
SIGNALS
FROM LPF
300µA
300µA
(IOOURT+QOUT+)
I(OOURT–QOUT–)
22k
STBY
(OR EN)
5546 F05
Figure 5. Simplified Circuit Schematic of I Channel
(or Q Channel) Outputs and STBY (or EN) Input
10
OPTIONAL
VCC3
C37
0.1µF
IOUT+ IOUT– QOUT+ QOUT–
R50
C35
2k
4.7µF
C36
R43
4.7µF
2k
5V
C38
0.1µF
C31
J1
R47
49.9Ω
1µF
6
IOUT
7 +3
U3
LT1818CS
4 –2
R48 C32
3.09k 1pF
C1
5.6pF
C34
R45 0.1µF
1k
R46
3.09k
R49
2k
C33
0.1µF
C27
0.1µF R41
1k
R39
3.09k
C2
5.6pF
C28
0.1µF
R42
2k
16 15 14 13
IOUT+ IOUT– QOUT+ QOUT–
3
7
U2
LT1818CS
2
4
C30
6
1µF R44
49.9Ω
J2
QOUT
C29 R40
1pF 3.09k
C43 T1, 1:4,TR-R
J3 22nF JTX-4-10T
MINI-CIRCUITS
IFIN
1
6
VCC1
1 GND
2 IF+
3 IF–
U1
LT5546
12
STBY
2XLO+ 11
2XLO– 10
T2, 1:4, TR-R C45
R35
JTX-4-10T 22nF J4
20k
MINI-CIRCUITS
2XLO
R52
240Ω
4 GND
9
EN
6
1
R36
20k
IF
VCC VCTRL DET VCC
567 8
17 GND
1 = EN
2 = STBY
C22
C16
C15
C39
1µF
1nF
1nF
1µF
VCC2
VCTRL
R51
100Ω
C25
1.5pF
OVERLOAD
SW1
C26 NOTE: OUTPUT BUFFERS U2 AND U3 WITH ASSOCIATED
1.8pF COMPONENTS ARE INCLUDED FOR EVALUATION ONLY.
DEMO BOARD: DC696A
C43, C45, C22, R51, C25, C26 AND C39 ARE OPTIONAL
5546 F04
Figure 6. Evaluation Circuit Schematic with I/Q Output Buffers
5546f
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