LTC1599 데이터 시트보기 (PDF) - Linear Technology
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LTC1599 Datasheet PDF : 20 Pages
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LTC1599
APPLICATIONS INFORMATION
Interfacing to the 68HC11
The circuit in Figure 7 is an example of using the 68HC11
to control the LTC1599. Data is sent to the DAC using two
8-bit parallel transfers from the controller’s Port B. The
WR signal is generated by manipulating the logic output
on Port A’s bit 3, the MLBYTE command is sent to the DAC
using Port A’s bit 4, and the LD command comes from the
SS output on Port D’s bit 5.
The sample listing 68HC11 assembly code in Listing A is
designed to emulate the Timing Diagram found earlier in
this data sheet. After variable declaration, the main portion
of the program retrieves the least significant byte from
memory, forces MLBYTE and WR to a logic low, and then
writes the low byte data to Port B. It then sets WR and
8-BIT PARALLEL
PORT B
68HC11
PORT A, BIT 3
PORT D, BIT 5
PORT A , BIT 4
LTC1599
WR LD MLBYTE
1599 F07
Figure 7. Using the 68HC11 to Control the LTC1599
MLBYTE high. Next, the most significant byte is copied
from memory and WR is again asserted low. The high byte
is written to Port B and WR is returned high. The transfer
of the 16 bits is completed by cycling the LD input low and
then high using the SS output on Port D.
************************************************************
*
*
* This example program uses 8-bit parallel port B, port A and port D *
* to transfer 16-bit parallel data to the LTC1599 16-bit current output *
* DAC. Port B at $1004 is used for two eight bit transfers. Port A,
*
* bit 3 is used for the LTC1599’s WR command and bit 4 is used for the *
* MLBYTE command. Port D’ SS output is used for the LTC1599’s LD *
* command
*
*
*
************************************************************
*
*****************************************
* 68HC11 register definitions
*
*****************************************
*
* PIOC EQU $1002 Parallel I/O control register
*
“STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB”
PORTA EQU $1000 Port A data register
*
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
PORTB EQU $1004 Port B data register
*
“Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0”
PORTD EQU $1008 Port D data register
*
“ - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD “
DDRD EQU $1009 Port D data direction register
SPCR EQU $1028 SPI control register
MBYTE EQU $00 This memory location holds the LTC1599’s bits 15 - 08
LBYTE EQU $01 This memory location holds the LTC1599’s bits 07 - 00
*
*****************************************
* Start OUTDATA Routine
*
*****************************************
*
ORG $C000 Program start location
INIT1 LDAA #$2F -,-,1,0;1,1,1,1
*
-, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAA PORTD Keeps SS* a logic high when DDRD, Bit5 is set
LDAA #$38 -,-,1,1;1,0,0,0
STAA DDRD SS* , SCK, MOSI are configured as Outputs
*
MISO, TxD, RxD are configured as Inputs
* DDRD’s Bit5 is a 1 so that port D’s SS* pin is a general output
sn1599 1599fs
17
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