LTC2615-1 데이터 시트보기 (PDF) - Linear Technology

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LTC2615-1

Octal 16-/14-/12-Bit Rail-to Rail DACs in 16-Lead SSOP

Linear Technology 

LTC2605/LTC2615/LTC2625

PIN FUNCTIONS

GND (Pin 1): Analog Ground.

VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog Volt-

age Output. The output range is 0V to VREF.

REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.

CA2 (Pin 7): Chip Address Bit 2. Tie this pin to VCC, GND

or leave it floating to select an I2C slave address for the

part (Table 2).

SCL (Pin 8): Serial Clock Input Pin. Data is shifted into

the SDA pin at the rising edges of the clock. This high

impedance pin requires a pull-up resistor or current

source to VCC.

SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted

into the SDA pin and acknowledged by the SDA pin. This

is a high impedance pin while data is shifted in. It is an

open-drain N-channel output during acknowledgment. This

pin requires a pull-up resistor or current source to VCC.

CA1 (Pin 10): Chip Address Bit 1. Tie this pin to VCC, GND

or leave it floating to select an I2C slave address for the

part (Table 2).

CA0 (Pin 11): Chip Address Bit 0. Tie this pin to VCC, GND

or leave it floating to select an I2C slave address for the

part (Table 2).

VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.

BLOCK DIAGRAM

GND 1

VOUT A 2

DAC A

DAC H

16 VCC

15 VOUT H

VOUT B 3

DAC B

DAC G

14 VOUT G

VOUT C 4

DAC C

DAC F

13 VOUT F

VOUT D 5

REF 6

CA2 7

SCL 8

DAC D

TIMING DIAGRAM

32-BIT SHIFT REGISTER

2-WIRE INTERFACE

DAC E

12 VOUT E

11 CA0

10 CA1

9

2605 BD01

SDA

10

SDA

tf

tLOW

tr

tSU(DAT)

tf

SCL

tHD(STA)

S

tHD(DAT)

tHIGH

tSU(STA)

S

ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS

Figure 1

tHD(STA)

tSP

tr

tBUF

tSU(STO)

P

S

2605 F01

2605fa

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