M24256-AEA6T(2001) 데이터 시트보기 (PDF) - STMicroelectronics
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M24256-AEA6T Datasheet PDF : 20 Pages
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Table 3. Device Select Code 1
Device Type Identifier
b7
b6
b5
b4
Device Select Code
1
0
1
0
Note: 1. The most significant bit, b7, is sent first.
M24256-A
Chip Enable
RW
b3
b2
b1
b0
0
E1
E0
RW
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9th clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
ther subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (0, E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
Up to four memory devices can be connected on a
single I2C bus. Each one is given a unique 2-bit
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the mem-
ory only responds if the Chip Select Code is the
same as the pattern applied to its Chip Enable
pins.
Table 4. Most Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8
Note: 1. b15 is treated as Don’t Care on the M24256-A series.
Table 5. Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
The 8th bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
ing the 9th bit time. If the memory does not match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 4) is sent first, followed by the Least significant
Byte (Table 5). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as Don’t
Care bits on the M24256-A memory.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory re-
Table 6. Operating Modes
Mode
RW bit
Current Address Read
1
0
Random Address Read
1
Sequential Read
1
Byte Write
0
Page Write
0
Note: 1. X = VIH or VIL.
WC 1
X
X
X
X
VIL
VIL
Data Bytes
Initial Sequence
1
START, Device Select, RW = 1
START, Device Select, RW = 0, Address
1
reSTART, Device Select, RW = 1
≥1
Similar to Current or Random Address Read
1
START, Device Select, RW = 0
≤ 64
START, Device Select, RW = 0
5/20
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