M2V56S20ATP-7UL 데이터 시트보기 (PDF) - Mitsumi
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M2V56S20ATP-7UL Datasheet PDF : 49 Pages
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SDRAM (Rev.1.01)
Single Data Rate
July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Power-Up Sequence and Intialize
CLK
/CS
/RAS
100µs
tRP
tRFC
tRFC
tRSC
/CAS
/WE
CKE
DQM
A0-9,11
MA
X
A10
0
X
A12
0
X
BA0,1
0
0
DQ
NOP
Power On
PRE ALL REFA
REFA
REFA
Minimum 8 REFA cycles
MRS ACT #0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
43
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