MAX195B 데이터 시트보기 (PDF) - Maxim Integrated
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MAX195B Datasheet PDF : 28 Pages
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16-Bit, 85ksps ADC with 10µA Shutdown
EOC
tCONV
tCSS
CS
tCSH
SCLK
(CASE 1)
SCLK
(CASE 2)
SCLK
(CASE 3)
DOUT
B15 B14 B13 B12 B11
B3 B2 B1
B0
MSB
tDV
tSD
LSB
tDH
CASE 1: SCLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: SCLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
CASE 3: SCLK IDLES HIGH, DATA LATCHED ON FALLING EDGE (CPOL = 1, CPHA = 0)
NOTE: ARROWS ON SCLK TRANSITIONS INDICATE LATCHING EDGE
Figure 7. Output Data Format, Reading Data Between Conversions (Mode 2)
+5V
10µF
CONVERSION
CLOCK
0.1µF
1 BP/UP/
SHDN
2 CLK
VDDA 16
VSSA 15
3 SCLK MAX195 AGND 14
4
VDDD
13
AIN
5 DOUT
6
DGND
7
EOC
8 CS
REF 12
11
VSSD
10
RESET
9
CONV
0.1µF
-5V
10µF
ANALOG
INPUT
REFERENCE
(0V TO VDDA)
Figure 8. MAX195 in the Simplest Operating Configuration
Data is clocked out on SCLK’s falling edge. Clock
data in on SCLK’s rising edge or, for clock speeds
above 2.5MHz, on the following falling edge to meet
the maximum SCLK-to-DOUT timing specification
(Figure 7). The maximum SCLK speed is 5MHz. See
the Operating Modes and SPI/QSPI Interfaces section
for additional information. When the conversion clock
is near its maximum (1.7MHz), reading the data after
each conversion (during the acquisition time) results
in lower throughput (about 70ksps max) than reading
the data during conversions, because it takes longer
than the minimum input acquisition time (four cycles
at 1.7MHz) to clock 16 data bits at 5Mbps. After the
data has been clocked in, leave some time (about
1µs) for any coupled noise on AIN to settle before
beginning the next conversion.
Whichever method is chosen for reading the data, con-
versions can be individually initiated by bringing CONV
low, or they can occur continuously by connecting EOC
to CONV. Figure 8 shows the MAX195 in its simplest
operational configuration.
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