MAX5580AEUP(2008) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX5580AEUP
(Rev.:2008)

Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs

Maxim Integrated 

Buffered, Fast-Settling, Quad,

12-/10-/8-Bit, Voltage-Output DACs

Table 1. Serial Write Data Format

MSB

16 BITS OF SERIAL DATA

CONTROL BITS

DATA BITS

C3 C2 C1 C0 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

tCH

SCLK

DIN

CS

tDS

C3

tCS0

tDH

tCSS

tCSW

tCL

C2

C1

tDO1

D0

tCSH

tCS1

DOUTDC1*

DOUT VALID

DOUTDC0

OR

DOUTRB*

tDO2

DOUT VALID

*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).

SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.

Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled)

tCL

SCLK

tDS

tCH

DIN

C3

C2

C1

tCS0

tDH

tCCS

CS

tCSW

tDSS

tDS0

DSP

D0

tCSH

tCS1

tDSW tDSPWL

tD02

DOUTDC0*

DOUT VALID

tD01

DOUTDC1

OR

DOUTRB*

DOUT VALID

*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).

SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.

Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled)

18 ______________________________________________________________________________________

LSB

D0

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