MBM29F017A-12 데이터 시트보기 (PDF) - Fujitsu

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MBM29F017A-12

FLASH MEMORY CMOS 16M (2M × 8) BIT

Fujitsu 

MBM29F017A-70/-90/-12

Write Operation Status

Table 7 Hardware Sequence Flags

Status

DQ7

DQ6

Embedded ProgramTM Algorithm

DQ7 Toggle

Embedded EraseTM Algorithm

0 Toggle

In progress

Erase

Suspended

Mode

Erase Suspend Read

(Erase Suspended Sector)

Erase Suspend Read

(Non-Erase Suspended Sector)

Erase Suspend Program

(Non-Erase Suspended Sector)

1

1

Data Data

DQ7

Toggle

(Note 1)

Embedded ProgramTM Algorithm

DQ7 Toggle

Exceeded

Time Limits

Embedded EraseTM Algorithm

Erase

Suspended

Mode

Erase Suspend Program

(Non-Erase Suspended Sector)

0 Toggle

DQ7 Toggle

DQ5

0

0

0

Data

0

1

1

1

DQ3

DQ2

0

1

1 Toggle

0 Toggle

Data Data

0

1

(Note 2)

0

1

1

N/A

0

N/A

Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic

“1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.

3. DQ0 and DQ1 are reserved pins for future use.

4. DQ4 is Fujitsu internal use only.

DQ7

Data Polling

The MBM29F017A device features Data Polling as a method to indicate to the host that the embedded algorithms

are in progress or completed. During the Embedded ProgramTM Algorithm, an attempt to read the device will

produce the complement of the data last written to DQ7. Upon completion of the Embedded ProgramTM Algorithm,

an attempt to read the device will produce the true data last written to DQ7. During the Embedded EraseTM

Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded

EraseTM Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data

Polling (DQ7) is shown in Figure 17.

Data polling will also flag the entry into Erase Suspend. DQ7 will switch “0” to “1” at the start of the Erase Suspend

mode. Please note that the address of an erasing sector must be applied in order to observe DQ7 in the Erase

Suspend Mode.

During Program in Erase Suspend, Data polling will perform the same as in regular program execution outside

of the suspend mode.

For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence.

For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling

must be performed at sector address within any of the sectors being erased and not a sector that is within a

protected sector group. Otherwise, the status may not be valid.

Just prior to the completion of Embedded Algorithm operation DQ7 may change asynchronously while the output

enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of

time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7

output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations

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