MC33596(2007) 데이터 시트보기 (PDF) - Freescale Semiconductor

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MC33596
(Rev.:2007)

PLL Tuned UHF Receiver for Data Transfer Applications

Freescale Semiconductor 

Supply Voltage Monitoring and Reset

GNDDIG, for decoupling. The supply voltage VCCDIG2 is equal to 1.6 V. In standby mode, this voltage

regulator goes into an ultra-low-power mode, but VCCDIG2 = 0.7 x VCCDIG. This enables the internal

registers to be supplied, allowing configuration data to be saved.

7 Supply Voltage Monitoring and Reset

At power-on, an internal reset signal is generated. All registers are reset.

When the LVDE bit is set, the low-voltage detection module is enabled. This block compares the supply

voltage on VCCINOUT with a reference level of about 1.8 V. If the voltage on VCCINOUT drops below

1.8 V, status bit LVDS is set. The information in status bit LVDS is latched and reset after a read access.

NOTE

If LVDE = 1, the LVD module remains enabled. The circuit cannot be put

in standby mode, but remains in LVD mode with a higher quiescent current,

due to the monitoring circuitry. LVD function is not accurate in standby

mode.

8 Receiver Functional Description

The receiver is based on a superheterodyne architecture with an intermediate frequency (IF) of 1.5 MHz

(see Figure 1). Its input is connected to the RFIN pin. Frequency down conversion is done by a high-side

injection I/Q mixer driven by the frequency synthesizer. An integrated poly-phase filter performs rejection

of the image frequency.

The low intermediate frequency allows integration of the IF filter providing the selectivity. The center

frequency is tuned by automatic frequency control (AFC) referenced to the crystal oscillator frequency.

Sensitivity is met by an overall amplification of approximately 96 dB, distributed over the reception chain,

comprising low-noise amplifier (LNA), mixer, post-mixer amplifier, and IF amplifier. Automatic gain

control (AGC), on the LNA and the IF amplifier, maintains linearity and prevents internal saturation.

Sensitivity can be reduced using four programmable steps on the LNA gain.

Amplitude demodulation is achieved by peak detection and comparison with a fixed or adaptive voltage

reference selected during configuration. Frequency demodulation is achieved in two steps: the IF amplifier

AGC is disabled and acts as an amplitude limiter; a filter performs a frequency-to-voltage conversion. The

resulting signal is then amplitude demodulated in the same way as in the case of amplitude modulation

with an adaptive voltage reference.

A low-pass filter improves the signal-to-noise ratio.

Shaped data are available if the integrated data manager is not used.

If used, the data manager performs clock recovery and decoding of Manchester coded data. Data and clock

are then available on the serial peripheral interface (SPI). The configuration sets the data rate range

managed by the data manager and the bandwidth of the low-pass filter.

An internal low-frequency oscillator can be used as a strobe oscillator to perform an automatic wakeup

sequence.

MC33596 Data Sheet, Rev. 3

Freescale Semiconductor

7

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