ML2340, ML2350
PIN CONNECTIONS
ML2340
ML2350
18-Pin DIP (P18)
VCC
VOUT
VZS
AGND
DGND
DB0
DB1
DB2
DB3
1
18
2
17
3
16
4
15
5
14
6
13
7
12
8
11
9
10
TOP VIEW
VREF IN
VREF OUT
GAIN 1
GAIN 0
XFER
DB7
DB6
DB5
DB4
ML2340
ML2350
18-Pin SOIC (S18W)
VCC
VOUT
VZS
AGND
DGND
DB0
DB1
DB2
DB3
1
18
2
17
3
16
4
15
5
14
6
13
7
12
8
11
9
10
TOP VIEW
VREF IN
VREF OUT
GAIN 1
GAIN 0
XFER
DB7
DB6
DB5
DB4
PIN DESCRIPTION
PIN NAME
1 VCC
2 VOUT
3 VZS
4 AGND
5 DGND
6 DB0
7 DB1
FUNCTION
Positive supply.
Voltage output of the D/A converter.
VOUT is referenced to VZS.
Zero Scale Voltage. VOUT is referenced
to VZS. VZS is normally tied to AGND
in the unipolar mode or to mid-supply
in the bipolar mode. When the device
is operated from a single power
supply, VZS has a maximum current
requirement of –300µA in the bipolar
mode.
Analog ground.
Digital ground. This is the ground
reference level for all digital inputs.
The range is AGND - DGND - VCC –
4.5V. DGND is normally tied to
system ground.
Data input — Bit 0 (LSB).
Data input — Bit 1.
PIN NAME
8 DB2
9 DB3
10 DB4
11 DB5
12 DB6
13 DB7
14 XFER
15 GAIN 0
16 GAIN 1
17 VREF OUT
18 VREF IN
FUNCTION
Data input — Bit 2.
Data input — Bit 3.
Data input — Bit 4.
Data input — Bit 5.
Data input — Bit 6.
Data input — Bit 7 (MSB).
Transfer enable input. The data is
transferred into the transparent latch at
the high level of XFER.
Digital gain setting input 0.
Digital gain setting input 1.
Voltage reference output. VREF OUT is
referenced to AGND. VREF OUT is set
to 2.5V and 5.0V in a low-voltage and
high-voltage operation, respectively
for the ML2350; 2.25V and 4.5V for
the ML2340.
Voltage reference input. VREF IN is
referenced to AGND.
2