¡ Semiconductor
MSM6669
• D0, D1, D2, D3
These are display data input pins. Display data is input in synchronization with a clock pulse.
Table 1 gives the relation between the display data, DF, liquid crystal drive output, and liquid
crystal display.
Display data
L
H
L
H
Table 1
DF
Liquid crystal drive output
Liquid crystal display
L
Non-select level
(V3)
OFF
L
Select level
(V1)
ON
H
Non-select level
(V4)
OFF
H
Select level
(VEE)
ON
• SHL
This is an input pin used to change the loading direction of display data.
Table 2 shows the correspondence between the bit positions of the 4-bit data (D0 to D3), its
loading direction, and driver outputs (O1 to O80).
Table 2
SHL
L
H
D0 → O1 → O5
D1 → O2 → O6
D2 → O3 → O7
D3 → O4 → O8
D0 → O80 → O76
D1 → O79 → O75
D2 → O78 → O74
D3 → O77 → O73
Direction of data loading
O77
O78
O79
O80
O4
O3
O2
O1
Last data
First data
8/9